Electrical and Computer Engineering Location: Online
Add to Calendar 2020-08-05T13:00:00 2020-08-05T13:00:00 America/New_York Doctoral Dissertation Proposal for Anjana Dissanayake Highly Reconfigurable Wakeup Receivers with Aggressive Duty-Cycling Techniques for High Density and Long-Range Internet-of-Things https://virginia.zoom.us/j/5041194068 Abstract: Online

Highly Reconfigurable Wakeup Receivers with Aggressive Duty-Cycling Techniques for High Density and Long-Range Internet-of-Things

https://virginia.zoom.us/j/5041194068

Abstract:

Ultra-low power sensor nodes are an essential building block for mass scale low-cost distributed sensing applications of Internet-of-Things. A typical sensor node consists of a digital processing unit, a wireless transceiver, and sensor interfaces, which under the continuous operation can quickly overwhelm the available power to the node due to high instantaneous power. The even-driven nature requires the nodes to respond in a non-scheduled manner which leads to unoptimized duty cycling if implemented with a local wakeup timer. An ultra-low power wakeup receiver which brings dedicated wireless-based on demand duty cycling capability with negligible power is an ideal solution to optimize the node power consumption.

To deliver cost efficient optimum power savings, wakeup receiver needs to maintain high sensitivity with low dc-power, robust operation with respect to interference for node coexistence, reconfigurability to adapt to process, temperature and post-deployment variations, and highly integratable to be a low-cost solution. The operating frequency also imposes several challenges as it leads to tradeoffs between power consumption, availability of high-quality factor components, antenna size and reusability, and available bandwidth. This research presents highly reconfigurable wakeup receiver design techniques and explore the limitations of two main aggressive duty cycling concepts with respect to total power consumption, latency of the wakeup, and sensitivity of the receiver.

The bit-level duty cycling technique has been implemented on a Tuned-RF receiver architecture in three proof of concept CMOS ICs operating at sub-GHz and explore the trade-off between the sensitivity, power, and latency.  The optimal tuning of RF signal integration, baseband signal processing, and overall startup time against the system duty-cycle with dedicated start-up and power-up pulses has been explored, which individually consider the faster RF and slower baseband circuit effects. Heterogenous integration with CMOS IC with MEMS resonators and high-Q off-chip inductors has been explored which benefit the overall sensitivity and interference performance. A novel IF channelization method for energy detector-based receivers without requiring a complex multi-tone transmission scheme has been used to demonstrate the multi-channel operation in a nano-watt scale wakeup receiver for the first time. The packet-level duty cycling technique has been investigated with a fully on-chip Uncertain-IF receiver architecture operating at 2.4GHz ISM band. A power efficient and duty-cycling friendly technique for synthesizing a robust RF reference frequency for down-conversion has been investigated which enables aggressive duty cycling for heterodyne based architectures.