Energy Efficient Computing at the Edge of the Network in the CMOS Era and Beyond
Recent advances in chip design have shown that analog computing can deliver energy-efficiencies that surpass traditional digital architectures and are very well suited to developing next-generation “smart” sensor systems. Such systems are widely applicable in areas like biomedical data acquisition, continuous infrastructure monitoring, intelligent sensor networks, and data analytics. However, implementing analog computing at scale requires principled techniques for algorithm-circuit co-design to robustly and reliably develop energy efficient systems.
In this talk we will cover applications of this principle ranging from communication and sensor interfaces to computational sub-blocks. We will first look at bounds on the energetic advantages derived through mixed-signal computing. I will then present an embodiment of these techniques in a micropower, multichannel, mixed-signal array processor developed in 65nm CMOS. I will then introduce a gradient-free variation of coordinate descent, that can deliver even greater energy efficiencies through algorithm-circuit co-design. I will conclude with some recent work spanning across various devices (FeFETs, RRAMs, and others), architectures (oscillator and compute-in memory) and emerging applications (smart sensors and neuromorphic computing). Crossing these hierarchies is critical for realizing the next generation of sensing, computing, and communicating systems.