Electrical and Computer Engineering Location: Thornton Hall E316, 2-3pm EST [in person seminar]
Add to Calendar 2024-03-29T14:00:00 2024-03-29T14:00:00 America/New_York ECE Seminar: Ram Krishnamurthy Ram Krishnamurthy Intel Labs, Intel Corporation Title: High-performance Energy-efficient Compute-in-Memory and AI accelerators for sub-18Å Technologies Thornton Hall E316, 2-3pm EST [in person seminar]

Ram Krishnamurthy

Intel Labs, Intel Corporation

Title: High-performance Energy-efficient Compute-in-Memory and AI accelerators for sub-18Å Technologies

Abstract: This presentation will highlight some of the emerging challenges and opportunities for sub-18Å process machine learning and AI technologies in the rapidly evolving IoT industry. With Moore’s law process technology scaling well into the nano-scale regime, future SoC platforms ranging from high performance cloud servers to ultra-low-power edge devices will demand advanced AI capabilities and energy-efficient deep neural networks. New and emerging IoT markets for autonomous vehicles, drones, and wearables require even higher performance at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient AI processors and SoCs in the sub-18Å technology nodes will be outlined. New paradigm shifts necessary for integrating special-purpose machine learning accelerators into next-generation SoCs will be explored. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for digital and analog in-memory and near-memory computing, reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic, memory and clocking circuits, AI inference accelerators including binary neural networks and associated on-chip interconnect fabric circuits are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.

Bio: Ram K. Krishnamurthy received the B.E. degree in electrical engineering from the National Institute of Technology, Trichy, India, in 1993, the M.S. degree in electrical and computer engineering from the State University of New York, Buffalo, NY, USA, in 1994, and the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, USA, in 1997. He has been at Intel Corporation since 1997. He is currently a Senior Principal Engineer at Intel Labs, Hillsboro, OR, USA, where he heads the High-Performance and Low-Voltage Circuits Research Group. In this role, he leads research in high-performance, energy-efficient, and low-voltage circuits for next generation microprocessors, accelerators, and Systems-On-Chip (SoCs). He has led circuit technology research directions in high speed arithmetic units, on-chip interconnects, reconfigurable computing, energy efficient clocking, ultra low voltage design, hardware security, compute-in-memory, neuromorphic computing, and machine learning accelerators. He has made circuit technology contributions to multiple generations of Intel’s data center, client, FPGA, IoT, and AI products spanning across 180nm to 7nm process technology nodes.

Krishnamurthy has filed 350 patents and holds 230 issued patents. He has published 200 papers and four book chapters on high-performance and energy-efficient circuits. He served as the Chair of the Semiconductor Research Corporation (SRC) Technical Advisory Board for the circuit design thrust. He served as the Technical Program Chair and the General Chair of the IEEE International Systems-on-Chip Conference and presently serves on the Conference’s Steering Committee. He is an Adjunct Faculty with the Electrical and Computer Engineering Department, Oregon State University, Corvallis, OR, USA, where he taught advanced VLSI design.

Krishnamurthy has received two Intel Achievement Awards for pioneering the first 64-bit Sparse-Tree ALU Technology and the first Advanced Encryption Standard hardware security accelerator on Intel products. He has received the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award, the IEEE European Solid State Circuits Conference Best Paper Award, the Outstanding Industry Mentor Award from SRC, Intel awards for most patents filed and most patents issued, the Intel Labs Gordon Moore Award, the Alumni Recognition Award from Carnegie Mellon University, the Distinguished Alumni Award from the State University of New York, MIT Technology Review’s TR35 Innovator Award, and was recognized as a top ISSCC paper contributor. He has served as a Distinguished Lecturer of the IEEE Solid-State Circuits Society, a Guest Editor of the IEEE Journal of Solid-State Circuits, an Associate Editor of the IEEE Transactions on VLSI Systems, and on the Technical Program Committees of ISSCC, CICC, and SOCC conferences. He is a Fellow of the IEEE.

Host: Dr. Mircea Stan and Dr. Mona Zebarjadi

Organizer: Dr. Cong Shen and Dr. Mona Zebarjadi