Title: Accelerating Complex Pattern Recognition Processing with In-Memory Accelerator Architectures
Newly available memory-centric architectures to accelerate finite automata-based pattern recognition have motivated use of automata processing in new applications. However, the existing automata processing solutions, including von Neumann and these new in-memory accelerators, are neither scalable nor efficient. Moreover, existing in-memory automata processing accelerators are unable to process more complex pattern structures such as tree and graph-shaped patterns.
This proposal outlines five new contributions to improve effectiveness of automata processing. This includes accelerating two applications using automata processing by developing novel algorithms and mapping them to in-memory automata processing accelerators: 1) frequent subtree mining, and 2) rule-based part-of-speech tagging in natural language processing. Based on the preliminary results from the above applications and their natural structures, and also by investigating the interconnect and scalability inefficiency in the exiting in-memory automata processing architectures, 3) we propose a reconfigurable high-speed, high-density, and low-power automata processing architecture with a compact, low-overhead, and yet flexible interconnect design. To evaluate our proposed architecture, we develop a cycle-accurate automata processing simulator, flexible enough to be adopted by other researchers for automata processing research.
Inspired by our study on pattern matching in tree-shaped structures, 4) we also propose a general-purpose, scalable, and reconfigurable memory-centric architecture for processing of tree-like data. We take inspiration from previous automata processing architectures, but support the richer deterministic pushdown automata computational model. Finally, motivated by the results and architectural features of our optimized automata processing architecture, the proposal investigates 5) the potential for a more specialized and high-speed in-memory hardware accelerator for bioinformatics computation.
Ashish Venkat (Chair)