Exploring New Attacks on the Intel/AMD Micro-Op Cache
Most modern processors translate instructions into simpler internal micro-ops for execution. This decoding process costs time and power, motivating architects to avoid it for repeatedly executed code by implementing a cache for decoded micro-ops. In this report, we conclude a project that explored the security implications of the micro-op cache. We worked with the recent Zen and Skylake architectures, performing a characterization study before successfully new attacks to abuse the micro-op cache. We also discuss potential defenses for such attacks.
- Kevin Skadron, Chair, (CS/SEAS/UVA)
- Ashish Venkat, Advisor, (CS/SEAS/UVA)
- Jack Davidson (CS/SEAS/UVA)
- Yonghwi Kwon (CS/SEAS/UVA)