Software Available
Software Available
Hundreds of Electronic Design Automation (EDA) tools are available. Click on the Vendors below to display. If you don't see your software under /app6 or /app7 directories on ECE Linux servers, you may send an email to engr-[email protected] to request a particular tool installed.
Cadence products support coursework, academic research, and advanced semiconductor design projects in areas including analog and RF ICs, digital VLSI, verification, system-on-chip (SoC) design, power electronics, high-speed PCB design, photonics, and advanced packaging. Licenses are available to authorized ECE users through the department's centralized license servers.
Cadence products are installed on ECE Linux servers, under /app7 (latest releases). Older releases are under /app6, /app3, /app2, and /app. Use older releases only when you are told to do so. You may email [email protected] to request a program installed or updated.
Run command 'source cadence-setup' before launching any Cadence tools to set up the license environment, among other environment variables.
Cadence Design Systems Product List
(Last update 9/8/2026, Gary Li)
Cadence provides a comprehensive suite of Electronic Design Automation (EDA) tools supporting the complete semiconductor, integrated circuit, package, PCB, and system design flow. The UVA ECE Cadence environment includes industry-standard tools for analog and mixed-signal design, digital synthesis and implementation, verification, physical verification, signal and power integrity analysis, PCB design, and advanced packaging. Available tools include:
- Virtuoso Platform for custom IC design, schematic capture, layout, analog and mixed-signal simulation, RF design, photonics, and advanced-node design.
- Spectre and AMS Designer for SPICE-level, mixed-signal, and high-performance circuit simulation.
- Genus for RTL synthesis and low-power optimization.
- Innovus for digital place-and-route, physical implementation, timing closure, and power-aware optimization.
- Tempus for static timing analysis and signoff.
- Voltus for power integrity, IR-drop, electromigration, and power analysis.
- Pegasus and Quantus for physical verification, DRC/LVS checking, parasitic extraction, and design signoff.
- Conformal for logical equivalence checking, ECO verification, and low-power verification.
- Modus for DFT insertion, ATPG, and scan test generation.
- Jasper Formal Verification Platform for formal property checking, linting, coverage analysis, and security verification.
- Xcelium and Verisium for digital, mixed-signal, and safety simulation, debugging, and verification management.
- Stratus HLS for high-level synthesis from C/C++/SystemC.
- Liberate for standard-cell characterization.
- Allegro X, OrCAD X, and PSpice for PCB design, electronic packaging, signal integrity, and circuit simulation.
- Sigrity, Clarity, EMX, Celsius, and related system analysis tools for electromagnetic, thermal, signal integrity, power integrity, and multi-physics simulation.
You will need to run command,
source synopsys-setup
to set up the license server environment before running any synopsys programs. You can also copy /app7/ece/bin/synopsys-setup script to your own directory and modify the script to fit your own needs.
Check here for the full list of products.
HEP Support 2021-IC Nanometer Design Bundle Software
We have access to products across physical verification, circuit simulation, digital implementation, verification, and analog/custom design.
Our Siemens EDA IC design bundle covers the flow from RTL simulation → synthesis → place & route → analog simulation → physical verification → yield analysis:
- Calibre Physical Verification Suite
- DRC, LVS, PERC, xRC, xACT, DesignReview, Pattern Matching, Yield tools
- Questa Verification Suite
- QuestaSim, Coverage, Assertions, Debug, Dataflow
- Eldo / T-Spice
- SPICE, FastSPICE, RF simulation, Verilog-AMS
- Precision Synthesis
- Logic synthesis, DFT, floorplanning, power optimization
- Aprisa
- Digital place-and-route
- Tanner / Pyxis Custom IC
- Schematic capture, IC layout, MEMS, photonics
Physical Verification (Calibre Suite)
| Feature | Product Name |
| calibredrc | Calibre DRC (Design Rule Checking) |
| calibrehdrc | Calibre Hierarchical DRC |
| calibrelvs | Calibre LVS (Layout vs. Schematic) |
| calibrehlvs | Calibre Hierarchical LVS |
| calibreperc | Calibre PERC (Electrical Reliability Verification) |
| calibrepercsp | Calibre PERC Specialized Checks |
| calibrexrc | Calibre xRC (Parasitic Extraction) |
| calibrexact | Calibre xACT |
| calibrexact3d | Calibre xACT 3D |
| calibrexrctoxact | Calibre xRC-to-xACT Flow |
| calibreqdb | Calibre Query Database (QDB) |
| calibreadp | Calibre Auto Debug Platform (ADP) |
| calinteractive | Calibre Interactive |
| caldfmproperty | Calibre DFM Property Checking |
| caldesignrev | Calibre DesignReview |
| calpmatch | Calibre Pattern Matching |
| calyieldanalyze | Calibre YieldAnalyzer |
| calyieldenhance | Calibre YieldEnhancer |
| calyieldserver | Calibre Yield Server |
| xcalibrate | Calibre xCalibrate |
Digital Simulation & Verification (Questa)
| Feature | Product Name |
| msimhdlsim | QuestaSim HDL Simulator |
| msimhdlmix | Questa Mixed-Language Simulation |
| msimcoverage | Questa Coverage |
| msimcompare | Questa Compare |
| msimviewer | Questa Visualizer / Wave Viewer |
| msimcdebug | Questa C Debug |
| msimdataflow | Questa Dataflow Analysis |
| msimpevsim | Questa Performance Verification Simulation |
| msimpevsimvlog | Questa Verilog Simulation |
| peproassertions | Questa Assertions / Property Checking |
Logic Synthesis & Physical Implementation (Aprisa / Precision)
| Feature | Product Name |
| psyncore | Precision Synthesis Core |
| psyndft | Precision DFT |
| psynfloorplan | Precision Floorplanning |
| psynpower | Precision Power Optimization |
| psynmxdb | Precision Multi-Database Support |
| pnrnitro | Aprisa Nitro Place-and-Route |
Analog / Mixed-Signal Simulation
| Feature | Product Name |
| eldokernel_c | Eldo Simulator Core |
| eldopsf | Eldo PSF Support |
| eldorfic | Eldo RF IC Option |
| edstspicex | T-Spice-X |
| edstspicevams | T-Spice Verilog-AMS |
| verilogacomp | Verilog-A Compiler |
| vhamsdev | Verilog-AMS Development |
| vhamsmod | Verilog-AMS Modeling |
| vhamsrt | Verilog-AMS Runtime |
Custom IC Design & Layout (Tanner / Analog FastSPICE)
| Feature | Product Name |
| edsdesign | Tanner S-Edit Design Capture |
| edssedit | S-Edit Schematic Editor |
| edsleditic | IC Layout Editing |
| edsleditphoto | Photonic Layout Editing |
| edsleditmems | MEMS Layout Editing |
| genieartist | Pyxis/Artist Custom Layout Environment |
| pnrtanner | Tanner Place-and-Route |
Administration & Infrastructure
| Feature | Product Name |
| admsrfic | Siemens EDA License Administration |
| secureip | Secure IP Support |
| verifdataport | Verification Data Port |
| xelga_c | ELGA Runtime Component |
| edsadvnode | Advanced Compute Node License |
| edshed | EDA Shared Environment / Infrastructure Component |
List of products:
- W2030UU Multi-Product Educational Support Package (contains ADS, GoldenGate, IC-CAP, GENESYS, SystemVue)
- W2101UU EMPro
- W2130UU Combined Product Package (includes both W2030UU and W2101UU)
- WW1500U Cliosoft SOS VDD University Bundle