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Ashish Venkat is an Assistant Professor in the Department of Computer Science at the University of Virginia, where he joined after obtaining a Ph.D. from UC San Diego. His research interests are in computer architecture and compilers, especially in instruction set design, processor microarchitecture, binary translation, code generation, and their intersection with computer security and machine learning. He is the recipient of NSF’s prestigious CAREER and CRII awards. His work has been published at top-tier venues such as ISCA, MICRO, ASPLOS, HPCA, and USENIX Security, and has received funding from NSF, DARPA, SRC, and Intel. His work has been recognized as an IEEE Micro Top Pick among all top-tier Computer Architecture Conference papers published in 2019, IEEE Design & Test Top Pick (twice) among all Hardware and Embedded Security papers published in Computer Architecture, Computer Security, and VLSI CAD conferences held in the last six years (in 2020 and 2021), best paper nominee at DATE 2023, and as the runner-up of the HPCA Best Paper Award in 2019. His dissertation research has been successfully ported and transferred to the Cloud Platforms division of the IBM Haifa Research Lab.

Research Interests

Computer Architecture
Computer Security

Selected Publications

Hardware Trojan Threats in eNVM Neuromorphic Devices. In Proceedings of the 26th Design, Automation and Test in Europe Conference (DATE 2023), Antwerp, Beliguim, April, 2023 [Acceptance Rate: 25%, Best Paper Nominee]. Lingxi Wu, Rahul Sreekumar, Rasool Sharifi, Kevin Skadron, Mircea Stan, Ashish Venkat
Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations. In Proceedings of the 55th ACM/IEEE International Symposium on Microarchitecture (MICRO 2022), Chicago, IL, October, 2022. [Acceptance Rate: 23%] Logan Moody, Wei Qi, Abdolrasoul Sharifi, Layne Berry, Joey Rudek, Jayesh Gaur, Jeff Parkhurst, Sreenivas Subramoney, Kevin Skadron, Ashish Venkat,
I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches. In Proceedings of the 48th ACM/IEEE International Symposium on Computer Architecture (ISCA), June, 2021. [ Acceptance rate: 19% ] Xida Ren, Logan Moody, Mohammadkazem Taram, Matthew Jordan, Dean M. Tullsen, Ashish Venkat
Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching. In Proceedings of the 48th ACM/IEEE International Symposium on Computer Architecture (ISCA), June, 2021. [ Acceptance rate: 19% ] Lingxi Wu, Rasool Sharifi, Marzieh Lenjani, Kevin Skadron, Ashish Venkat
CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities. In Proceedings of the 47th ACM International Symposium on Computer Architecture (ISCA), June, 2020. [Acceptance Rate: 18%] Rasool Sharifi and Ashish Venkat
Packet Chasing: Observing Network Packets over a Cache Side-Channel. In Proceedings of the 47th ACM International Symposium on Computer Architecture (ISCA), June, 2020. [Acceptance Rate: 18%] Mohammadkazem Taram, Ashish Venkat, and Dean M. Tullsen
Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management. In IEEE Micro, Special Issue on the Top Picks from the Computer Architecture Conferences (IEEE Micro Top Picks), May, 2019. Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen
Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization. In Proceedings of the 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2019), April, 2019. Mohammadkazem Taram, Ashish Venkat, and Dean M. Tullsen
Composite-ISA Cores: Enabling Multi-ISA Heterogeneity using a Single ISA. In Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture (HPCA 2019), February, 2019. [Best Paper Nominee] [Acceptance Rate: 21%] Ashish Venkat, Harsha Basavaraj, Dean M. Tullsen
"Reliability-Aware Data Placement for Heterogeneous Memory Architecture." In Proceedings of the 24th IEEE International Symposium on High Performance Computer Architecture (HPCA 2018), Vienna, Austria, February 2018 [Acceptance Rate: 21%] Manish Gupta, Vilas Sridharan, David Roberts, Andreas Prodromou, Ashish Venkat, Dean M. Tullsen, and Rajesh Gupta
Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor. In Proceedings of the 41st International Symposium on Computer Architecture (ISCA 2014), Minneapolis, MN, June 2014 [Acceptance Rate: 18%] Ashish Venkat and Dean M. Tullsen

Courses Taught

CS 6501 - Hardware Security Fall 2018
CS 3330 - Undergraduate Computer Architecture Spring 2019
CS 6354 - Graduate Computer Architecture Fall 2019


NSF CAREER Award 2023
DATE Best Paper Nomination 2023
Top Pick in Hardware and Embedded Security 2020 and 2021
IEEE Micro Top Pick 2019
HPCA Best Paper Runner-Up 2019
NSF CRII Award 2018

Featured Grants & Projects

NSF CAREER: Enabling Robust and Adaptive Architectures through a Decoupled Security-Centric Hardware/Software Stack The growing complexity in modern systems has placed substantial limits on our ability to comprehensively assess threats and deploy timely mitigations. According to Google's Project Zero, a new exploit is discovered in the wild every 17 days, although it takes an average of 15 days across all vendors to patch a vulnerability, highlighting the inability of existing solutions to scale with the rapidly evolving threat landscape. This project takes a radically new approach by developing a holistic security-centric hardware/software stack that is decoupled from the Instruction Set Architecture (ISA), so as to empower software to dynamically push expressive security policies to hardware, where they can be transparently and efficiently enforced on-demand and in-the-field through novel hardware design mechanisms, without the need for recompilation, redeployment, and frequent hardware upgrades. This work is expected to significantly enhance robustness, versatility, flexibility, and adaptability of modern architectures in the range and types of exploits they can mitigate, while simultaneously minimizing both the time to mitigation and the cost of deployment. This project will also address the urgent need to boost the nation's cybersecurity workforce through (a) curriculum development and ethical hacking workshops targeted at high school, college, and professional students, (b) development of community research infrastructure and evaluation testbeds for rapid assessment of security policies, and (c) research mentorship of undergraduate and underrepresented students on security-related projects. This project entails three synergistic research thrusts that together enable a holistic full system across-the-stack solution for timely mitigation of exploits. The first thrust will develop a decoupled security-centric hardware/software interface to allow software to capture interactions and relationships among the different subjects and objects in the system and specify an expressive set of security policies in the form of logic formulas, to mitigate a wide range of hardware and software attacks ranging from memory and type safety to transient execution attacks. The second thrust will develop novel hardware design mechanisms and microcode primitives to evaluate and enforce the security policies specified in software, while maintaining high levels of performance with minimal impact on power and area. The third thrust will develop innovative hardware-based attribute tracking mechanisms to transparently track the flow of high-level software attributes, during execution, to enhance the effectiveness of the underlying hardware enforcement mechanisms.
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NSF/Intel FoMR: Speculative Super-optimization: Boosting Performance via Speculation-Driven Dynamic Binary Optimization Modern processors are characterized by increasing core counts, and yet, a substantial chunk of software applications is inherently sequential. Although modern compilers feature sophisticated optimizations, significant wasteful computation still persists due to computational patterns that are unpredictable at compile-time. This project explores techniques to deploy aggressive speculative dynamic binary optimizations within the processor, enabling continuous optimization of inherently sequential code. This work addresses a pressing need for systems that can aggressively and yet seamlessly super-optimize machine code, adapting to the dynamic execution environment, and thereby speed up inherently sequential applications.
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SRC CADT: ProxyVM: A Scalable and Re-Targetable Compiler Framework for Privacy-Preserving Machine Learning This research proposes ProxyVM, a scalable and a retargetable compiler framework that enables privacy-aware synthetic workload generation with high performance predictability. The key to ProxyVM is a privacy-preserving performance outline, a rich intermediate representation akin to TensorFlow’s computation graph, generated by a performance characterizing front-end deployed at the customer site, allowing the performance characteristics of a sensitive workload to be seamlessly shared with hardware vendors, with the guarantee that proprietary algorithms and sensitive user data remain invulnerable to disclosure. This privacy-preserving performance outline is designed for rich expressiveness allowing workloads to be characterized as a set of computational chunks or algorithms of varying granularity, parameterizable by input data attributes that are potentially deidentified/obfuscated via differential privacy techniques. ProxyVM’s backends, deployed at the hardware manufacturer’s end, may then leverage this outline to automatically generate synthetic workloads that retain the performance characteristics of the real workload and further guide application-specific hardware design.
NSF:CRII:SaTC: Mitigating Software-Based Microarchitectural Attacks via Secure Microcode Customization Modern high-performance processors implement complex microarchitectural optimizations involving speculative execution which has recently been shown to be vulnerable to a type of malicious attack called Spectre. This project will investigate a microarchitectural solution framework to secure against such attacks. This framework, called context-sensitive fencing, will seek to automatically track and detect malicious execution patterns dynamically to trigger defense code without programmer intervention and with minimal impact on processor performance.
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DARPA:MTO: Mobilizing the Micro-Ops: Securing Processor Architectures via Context-Sensitive Decoding This project explores techniques that combine a low-cost, configurable, transparent defense mechanism (based on context-sensitive decoding) with an effective learning-based detection model, which allows us to minimize the cost of secure computation by constantly adapting the level of defense, and targeting the type of defense, to the current execution characteristics and the current likelihood and type of attack.
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NSF Student Travel Grant for the 26th IEEE International Symposium on High Performance Computer Architecture (HPCA 2020) This award will support approximately 25 students to attend 2020 International Symposium on High-Performance Computer Architecture (HPCA) to be located in San Diego, CA, USA from February 22 - 26, 2020. HPCA is widely recognized as one of the top-tier conferences in the field of Computer Architecture and has attendees from academia, both students and faculty, and from the industry. Students who attend the conference will be exposed to intellectually stimulating research by attending the many talks, panels, keynotes, and poster presentations at the conference.
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