Bio

Ph.D. in Computer Science, University of California, San Diego

"Towards Architecture-Aware Code and Program-Aware Architectures"

Ashish Venkat is an Assistant Professor in the Department of Computer Science at the University of Virginia, where he joined after obtaining a Ph.D. from UC San Diego.  His research interests are in computer architecture and compilers, especially in instruction set design, processor microarchitecture, binary translation, code generation, and their intersection with computer security and machine learning.  His work on heterogeneous architectures has been published at top-tier venues such as ISCA, ASPLOS, and HPCA.  His work has been featured in the IEEE Micro Top Picks Issue of 2019 and was recognized as the runner-up of the HPCA Best Paper Award in 2019.  His dissertation research has been successfully ported and transferred to the Cloud Platforms division of the IBM Haifa Research Lab.

Awards

  • NSF CRII Award 2018
  • IEEE Micro Top Pick 2019
  • HPCA Best Paper Runner-Up 2019

Research Interests

  • Computer Architecture
  • Compilers
  • Computer Security

Selected Publications

  • Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management. In IEEE Micro, Special Issue on the Top Picks from the Computer Architecture Conferences (IEEE Micro Top Picks), May, 2019. Mohammadkazem Taram, Ashish Venkat, Dean M. Tullsen
  • Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization. In Proceedings of the 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2019), April, 2019. Mohammadkazem Taram, Ashish Venkat, and Dean M. Tullsen,
  • Composite-ISA Cores: Enabling Multi-ISA Heterogeneity using a Single ISA. In Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture (HPCA 2019), February, 2019. Ashish Venkat, Harsha Basavaraj, Dean M. Tullsen
  • "Mobilizing the Micro-Ops: Exploiting Context-Sensitive Decoding for Security and Energy Efficiency, " In Proceedings of the 45th International Symposium on Computer Architecture (ISCA 2018), Los Angeles, CA, June 2018. Mohammadkazem Taram, Ashish Venkat, and Dean M. Tullsen
  • "Reliability-Aware Data Placement for Heterogeneous Memory Architecture." In Proceedings of the 24th IEEE International Symposium on High Performance Computer Architecture (HPCA 2018), Vienna, Austria, February 2018 Manish Gupta, Vilas Sridharan, David Roberts, Andreas Prodromou, Ashish Venkat, Dean M. Tullsen, and Rajesh Gupta
  • HIPStR: Heterogeneous-ISA Program State Relocation. In Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2016), Atlanta, GA, April 2016. Ashish Venkat, Sriskanda Shamasunder, Hovav Shacham, and Dean M. Tullsen.
  • Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor. In Proceedings of the 41st International Symposium on Computer Architecture (ISCA 2014), Minneapolis, MN, June 2014 Ashish Venkat and Dean M. Tullsen.
  • Execution Migration in a Heterogeneous-ISA Chip Multiprocessor. In Proceesings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2012), London, UK, March, 2012. Matthew DeVuyst, Ashish Venkat, and Dean M. Tullsen

Courses Taught

  • CS 6501 - Hardware Security Fall 2018
  • CS 3330 - Undergraduate Computer Architecture Spring 2019
  • CS 6354 - Graduate Computer Architecture Fall 2019

Featured Grants & Projects

  • NSF:CRII:SaTC: Mitigating Software-Based Microarchitectural Attacks via Secure Microcode Customization


    Modern high-performance processors implement complex microarchitectural optimizations involving speculative execution which has recently been shown to be vulnerable to a type of malicious attack called Spectre. This project will investigate a microarchitectural solution framework to secure against such attacks. This framework, called context-sensitive fencing, will seek to automatically track and detect malicious execution patterns dynamically to trigger defense code without programmer intervention and with minimal impact on processor performance.

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  • NSF/Intel FoMR: Speculative Super-optimization: Boosting Performance via Speculation-Driven Dynamic Binary Optimization


    Modern processors are characterized by increasing core counts, and yet, a substantial chunk of software applications is inherently sequential. Although modern compilers feature sophisticated optimizations, significant wasteful computation still persists due to computational patterns that are unpredictable at compile-time. This project explores techniques to deploy aggressive speculative dynamic binary optimizations within the processor, enabling continuous optimization of inherently sequential code. This work addresses a pressing need for systems that can aggressively and yet seamlessly super-optimize machine code, adapting to the dynamic execution environment, and thereby speed up inherently sequential applications.

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  • DARPA:MTO: Mobilizing the Micro-Ops: Securing Processor Architectures via Context-Sensitive Decoding


    This project explores techniques that combine a low-cost, configurable, transparent defense mechanism (based on context-sensitive decoding) with an effective learning-based detection model, which allows us to minimize the cost of secure computation by constantly adapting the level of defense, and targeting the type of defense, to the current execution characteristics and the current likelihood and type of attack.

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