Ashish Venkat

The growing complexity in modern systems has placed substantial limits on our ability to comprehensively assess threats and deploy timely mitigations. According to Google's Project Zero, a new exploit is discovered in the wild every 17 days, although it takes an average of 15 days across all vendors to patch a vulnerability, highlighting the inability of existing solutions to scale with the rapidly evolving threat landscape. This project takes a radically new approach by developing a holistic security-centric hardware/software stack that is decoupled from the Instruction Set Architecture (ISA), so as to empower software to dynamically push expressive security policies to hardware, where they can be transparently and efficiently enforced on-demand and in-the-field through novel hardware design mechanisms, without the need for recompilation, redeployment, and frequent hardware upgrades. This work is expected to significantly enhance robustness, versatility, flexibility, and adaptability of modern architectures in the range and types of exploits they can mitigate, while simultaneously minimizing both the time to mitigation and the cost of deployment. This project will also address the urgent need to boost the nation's cybersecurity workforce through (a) curriculum development and ethical hacking workshops targeted at high school, college, and professional students, (b) development of community research infrastructure and evaluation testbeds for rapid assessment of security policies, and (c) research mentorship of undergraduate and underrepresented students on security-related projects. This project entails three synergistic research thrusts that together enable a holistic full system across-the-stack solution for timely mitigation of exploits. The first thrust will develop a decoupled security-centric hardware/software interface to allow software to capture interactions and relationships among the different subjects and objects in the system and specify an expressive set of security policies in the form of logic formulas, to mitigate a wide range of hardware and software attacks ranging from memory and type safety to transient execution attacks. The second thrust will develop novel hardware design mechanisms and microcode primitives to evaluate and enforce the security policies specified in software, while maintaining high levels of performance with minimal impact on power and area. The third thrust will develop innovative hardware-based attribute tracking mechanisms to transparently track the flow of high-level software attributes, during execution, to enhance the effectiveness of the underlying hardware enforcement mechanisms.

Modern processors are characterized by increasing core counts, and yet, a substantial chunk of software applications is inherently sequential. Although modern compilers feature sophisticated optimizations, significant wasteful computation still persists due to computational patterns that are unpredictable at compile-time. This project explores techniques to deploy aggressive speculative dynamic binary optimizations within the processor, enabling continuous optimization of inherently sequential code. This work addresses a pressing need for systems that can aggressively and yet seamlessly super-optimize machine code, adapting to the dynamic execution environment, and thereby speed up inherently sequential applications.

Modern high-performance processors implement complex microarchitectural optimizations involving speculative execution which has recently been shown to be vulnerable to a type of malicious attack called Spectre. This project will investigate a microarchitectural solution framework to secure against such attacks. This framework, called context-sensitive fencing, will seek to automatically track and detect malicious execution patterns dynamically to trigger defense code without programmer intervention and with minimal impact on processor performance.

This project explores techniques that combine a low-cost, configurable, transparent defense mechanism (based on context-sensitive decoding) with an effective learning-based detection model, which allows us to minimize the cost of secure computation by constantly adapting the level of defense, and targeting the type of defense, to the current execution characteristics and the current likelihood and type of attack.

This award will support approximately 25 students to attend 2020 International Symposium on High-Performance Computer Architecture (HPCA) to be located in San Diego, CA, USA from February 22 - 26, 2020. HPCA is widely recognized as one of the top-tier conferences in the field of Computer Architecture and has attendees from academia, both students and faculty, and from the industry. Students who attend the conference will be exposed to intellectually stimulating research by attending the many talks, panels, keynotes, and poster presentations at the conference.