Bio

B.S. in Electrical & Computer Engineering, B.A. in Economics,​ Rice University, 1994Ph.D. ​in Computer Science, Princeton University, 1999

"Our group's work focuses on near-data processing and more generally on how to design microprocessors, hardware accelerators, and memory devices for speed, energy efficiency, thermal management, and reliability."

Kevin Skadron, Harry Douglas Forsyth Professor of Computer Science

 

Research interests include:

Computer Architecture, Hardware Acceleration, Near-data/in-memory Processing, Automata Processing, High-Performance Computing, Low Power Design, and Hardware Support for Debugging

 

 

Kevin Skadron has been on the faculty at University of Virginia since 1999. He received his B.S. in Electrical and Computer Engineering and B.A. in Economics from Rice University in 1994, and his Ph.D. in Computer Science from Princeton University in 1999. He spent the 2007-08 academic year on sabbatical at NVIDIA Research. He served as department chair from 2012-2021. He also helped found and serves as director for the Center for Automata Processing (CAP) and the Center for Research on Intelligent Storage and Processing in Memory (CRISP). He is also a member of the Center for Research on Processing in Storage and Memory (PRISM), part of the JUMP 2.0 program. Skadron is the recipient of the 2011 ACM SIGARCH Maurice Wilkes Award and a Fellow of the IEEE and ACM. For the year 2003-04, he was named a University of Virginia Teaching Fellow. Among other professional activities, he is co-founder and editorial board member of IEEE Computer Architecture Letters, for which he served as associate editor-in-chief from 2001-2009 and editor-in chief from 2010-2012. He has served on the editorial board of IEEE Micro from 2004-2012 and as co-founder/co-editor (with Kevin Rudd) of its "Prolegomena" column, as secretary-treasurer of ACM's SIGARCH from 2007-2011, as technical program co-chair of PACT 2006, general co-chair for PACT 2002 and MICRO-37, and on numerous technical program committees. He has also given several conference keynotes.

Awards

  • ACM SIGARCH Maurice Wilkes Award 2011
  • Fellow of the IEEE
  • Fellow of the ACM

Research Interests

  • Computer Architecture
  • Cloud/High-performance Computing
  • Low Power Design
  • Automata Processing

Selected Publications

  • “ACTS: A Near-Memory FPGA Graph Processing Framework.” Proceedings of the IEEE International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2023. O. Jaiyeoba and K. Skadron
  • “DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching.” IEEE Computer Architecture Letters, 21(2):89-92, July-Dec. 2022. L. Wu, R. Sharifi, A. Venkat, and K. Skadron.
  • “Pulley: An Algorithm/Hardware Co-optimization for In-memory Sorting.” IEEE Computer Architecture Letters, 21(2):109-112, July-Dec. 2022. M. Lenjani, A. Ahmed, and K. Skadron.
  • "Synthesizing Legacy String Code for FPGAs Using Bounded Automata Learning." IEEE Micro special issue on Compiling for Accelerators,” 42(5):70-77, Sep.-Oct. 2022. K. Angstadt, T. Tracy, J.-B. Jeannin, K. Skadron, and W. Weimer.
  • “Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations.” In Proceedings of the ACM/IEEE International Symposium on Microarchitecture (MICRO), Oct. 2022. L. Moody, W. Qi,* A. Sharifi, L. Berry,* J. Rudek, J. Gaur, J. Parkhurst, S. Subramoney, K. Skadron, A. Venkat.
  • “Gearbox: A Case for Supporting Accumulation Dispatching and Hybrid Partitioning in PIM-based Accelerators.” In Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2022. M. Lenjani, A. Ahmed, M. R. Stan, and K. Skadron.
  • “From 2.5D to 3D Chiplet Systems: Investigation of Thermal Implications with HotSpot 7.0.” In Proceedings of the IEEE/ASME Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), May 2022. J.-H. Han, X. Guo, K. Skadron, and M. R. Stan.
  • “PiMulator: A Fast and Flexible Processing-in-Memory Emulation Platform.” In Proceedings of the ACM/IEEE/EDAA/EDAC Conference on Design, Automation and Test in Europe (DATE), Mar. 2022. S. Mosanu, M. N. Sakib, T. Tracy III, E. Cukurtas, A. Ahmed, P. Ivanov, S. Khan, K. Skadron, M. Stan.
  • “Supporting Moderate Data Dependency, Position Dependency, and Divergence in PIM-based Accelerators.” IEEE Micro special issue on Processing in Memory, Jan/Feb. 2022, 42(1):108-115. DOI 10.11 M. Lenjani and K. Skadron.
  • “Sunder: Enabling Low-Overhead and Scalable Near Data Pattern Matching Acceleration.” In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO), Oct. 2021. E. Sadredini, R. Rahimi, M. Imani, and K. Skadron.
  • “Ultra Efficient Acceleration for De Novo Genome Assembly via Near-Memory Computing.” In Proceedings of the ACM/IEEE/IFIP International Conference on Parallel Architectures and Compiler Techniques (PACT), Sept. 2021. (To appear.) M. Zhou, L. Wu, M. Li, N. Moshiri, K. Skadron, and T. Rosing.
  • “Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching.” In Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2021. ABS L. Wu, R. Sharifi, M. Lenjani, K. Skadron, and A. Venkat.
  • “BigMap: Future-proofing Fuzzers with Efficient Large Maps.” In Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2021. ABS A. Ahmed, J. Hiser, A. Nguyen-Tuong, J. W. Davidson, and K. Skadron.
  • “Runtime Verification on FPGAs with LTLf Specifications.” In Proceedings of the Formal Methods in Computer-Aided Design (FMCAD), Sept. 2020 ABS T. Tracy II, L. Tabajara, M. Vardi, and K. Skadron.
  • “Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAs.” In Proceedings of the IEEE International Symposium on Field Customizable Computing Machines (FCCM), May 2020. ABS R. Rahimi, E. Sadredini, M. Stan, and K. Skadron.
  • “FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators.” In Proceedings of the ACM International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Mar. 2020. ABS E. Sadredini, R. Rahimi, M. Lenjani, M. Stan, and K. Skadron.
  • “Fulcrum: a Simplified Control and Access Mechanism toward Flexible and Practical In-Situ Accelerators.” In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2020. ABS M. Lenjani, P. Gonzalez, E. Sadredini, S. Li, Y. Xie, A. Akel, S. Eilert, M. R. Stan, and K. Skadron.
  • “Hopscotch: A Micro-benchmark Suite for Memory Performance Evaluation.” In Proceedings of the International Symposium on Memory Systems (MEMSYS), Sep.-Oct. 2019. ABS A. Ahmed, K. Skadron.
  • “GraphTinker: A High Performance Data Structure for Dynamic Graph Processing.” In Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2019. ABS O. Jaiyeoba and K. Skadron.
  • “Debugging Support for Pattern-Matching Languages and Accelerators.” In Proceedings of the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Apr. 2019. ABS M. Casias, K. Angstadt, T. Tracy II, K. Skadron, and W. Weimer.
  • “ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata.” In Proceedings of the ACM/IEEE International Symposium on Microarchitecture (MICRO), Oct. 2018. ABS K. Angstadt, A. Subramaniyan, E. Sadredini, R. Rahimi, W. Weimer, K. Skadron, and R. Das.
  • “A Scalable Solution for Rule-Based Part-of-Speech Tagging on Novel Hardware Accelerators.” In Proceedings of the ACM SIGKDD Conference on Knowledge Discovery and Data Mining (KDD), Aug. 2018. ABS E. Sadredini, D. Guo, C. Bo, R. Rahimi, K. Skadron, and H. Wang.
  • “Characterizing and Mitigating Output Reporting Bottlenecks in Spatial-Reconfigurable Automata Processing Architectures.” In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2018. ABS J. Wadden, K. Angstadt, and K. Skadron.
  • “Searching for Potential gRNA Off-Target Sites for CRISPR/Cas9 using Automata Processing across Different Platforms.” In Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2018. ABS C. Bo, V. Dang, E. Sadredini, K. Skadron.
  • “MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem.” IEEE Computer Architecture Letters, Dec. 2017. ABS K. Angstadt, J. Wadden, V. Dang, T. Xie, D. Kramp, W. Weimer, M. Stan, and K. Skadron.
  • “Frequent Subtree Mining on the Automata Processor: Challenges and Opportunities.” In Proceedings of the ACM International Conference on Supercomputing (ICS), June 2017. ABS E. Sadredini, K. Wang, and K. Skadron.
  • “Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems.” Journal of Signal Processing Systems, Springer, published online Nov. 2016. DOI 10.1007/s11265-016-1199-1. ABS M. El-Hadedy, X. Guo, M. Margala, M. R. Stan, and K. Skadron.
  • "Lumos+: Rapid, Pre-RTL Design Space Exploration on Accelerator-Rich Heterogeneous Architectures with Reconfigurable Logic." In Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2016. ABS L. Wang and K. Skadron.
  • “AutomataZoo: A Modern Automata Processing Benchmark Suite.” In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Oct. 2018. ABS J. Wadden, T. Tracy II, E. Sadredini, L. Wu, C. Bo, J. Du, Y. Zhou, M. Wallace, J. Udall, M. Stan, and K. Skadron.
  • "Sequential Pattern Mining with the Micron Automata Processor." In Proceedings of the ACM International Conference on Computing Frontiers, May 2016. Best paper award! ABS K. Wang, E. Sadredini, and K. Skadron. (Best paper award)
  • "RAPID Programming of Pattern-Recognition Processors." In Proceedings of the ACM International Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Apr. 2016. ABS K. Angstadt, W. Weimer, and K. Skadron.
  • "A 16-bit Reconfigurable Encryption Processor for Pi-Cipher." In Proceedings of the 23rd Reconfigurable Architectures Workshop (RAW), in conjunction with IPDPS, May 2016. Best paper award! ABS M. El-Hadedy, H. Mihajloska, D. Gligoroski, A. Kulkarni, D. Stroobandt and K. Skadron. (Best paper award)
  • "Transient Voltage Noise in Charge-Recycled Power Delivery Networks for Many-Layer 3D-IC." In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2015. ABS R. Zhang, K. Mazumder, B. H. Meyer, K. Wang, K. Skadron, and M. R. Stan.
  • "Architecture Implications of Pads as a Scarce Resource." In Proceedings of the ACM/IEEE International Symposium on Computer Architecture, June 2014. ABS R. Zhang, K. Wang, B. H. Meyer, M. R. Stan, and K. Skadron.
  • "Dymaxion++: A Directive-based API to Optimize Data Layout and Memory Mapping for Heterogeneous Systems." In Proceedings of the Fourth International Workshop on Accelerators and Hybrid Exascale Systems, in conjunction with IPDPS, May 2014. ABS S. Che, J. Meng, and K. Skadron.
  • "Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading." In Proceedings of the ACM/IEEE International Symposium on Computer Architecture, June 2014. J. Wadden, A. Lyashevsky, S. Gurumurthi, V. Sridharan, and K. Skadron.
  • "Implications of the Power Wall: Dim Cores and Reconfigurable Logic." IEEE Micro special issue on Dark Silicon, 33(5): 40-49, Sept.-Oct. 2013.DOI 10.1109/MM.2013.74. ABS L. Wang and K. Skadron.
  • "Robust SIMD: Dynamically Adapted SIMD Width and Multi-Threading Depth." In Proceedings of the IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 2012. J. Meng, J. W. Sheaffer, and K. Skadron.
  • "Federation: Boosting Per-Thread Performance of Throughput-Oriented Manycore Architectures." ACM Transactions on Architecture and Code Optimization (TACO), 7(4):1-38, Dec. 2010, DOI 10.1145/1880043.1880046. M. Boyer, D. Tarjan, K. Skadron.
  • "The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches." In Proceedings of theACM/IEEE International Conference for High Performance Computing, Networking, Sto D. Tarjan and K. Skadron.
  • "Accurate, Pre-RTL Temperature-Aware Processor Design Using a Parameterized, Geometric Thermal Model." IEEE Transactions on Computers, 57(9):1277-88, Sept. 2008, DOI 10.1109/TC.2008.64 W. Huang, K. Sankaranarayanan, K. Skadron, R. J. Ribando, and M. R. Stan.
  • "Scalable Parallel Programming with CUDA." ACM Queue, 6(2):40-53, Mar.-Apr. 2008. DOI 10.1145/1365490.1365500 J. Nickolls, I. Buck, M. Garland, K. Skadron.
Google Scholar

Courses Taught

  • CS 433: Advanced Computer Architecture fall 2005; spring 2007; spring 2009
  • CS 414/4414: Operating Systems spring 2002, 2004, 2005, 2006, fall 2008, fall 2010, spring 2012, fall 2022, fall 2023
  • CS 6501: Special Topics in Computer Architecture: Hardware Accelerators - Past, Present, and Future Spring 2023
  • CS 6190: Computer Science Perspectives fall 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020
  • CS 6354 (formerly 654): Graduate Computer Architecture fall 2000, 2001, 2002, 2003, 2004, 2009, and spring 2013, 2014
  • CS 6501: Special Topics in Computer Architecture: Heterogeneous and Scalable Computing fall 2011
  • CS 754: Advanced Computer Architecture (Multicore Architectures and Programming Models) fall 2006
  • CS 851/8501: Special Topics in Computer Architecture fall 1999, spring 2000, spring 2001, spring 2002, fall 2004, most recently spring 2010
  • CS 8535: Advanced Computer Architecture: Dark Silicon spring 2011

Featured Grants & Projects

  • Current Grants and Acknowledgements

    This work is currently supported by the US National Science Foundation (NSF) under grant PPoSS-2217071grants from the Laboratory for Physical Sciences; grants from the SRC Global Research Corporation; grants from the MIST NSF Industry/University Research Center; CRISP, one of six centers in JUMP 1.0, a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and PRISM, one of seven centers in JUMP 2.0, a Semiconductor Research Corporation program sponsored by MARCO and DARPA.