Location
Rice Hall 512 ​PO Box 400743
Link Lab Multi-functional Integrated System Technology (MIST) IUCRC Center Center for Hardware and Embedded Systems Security and Trust (CHEST) IUCRC Center Center for Automata Processing (CAP) High Performance Low Power (HPLP)

About

Mircea R. Stan is teaching and doing research in the areas of AI hardware, Processing in Memory, Cyber-Physical Systems, Computational RFID, Low Power, Spintronics, and Nanoelectronics. He leads the High-Performance Low-Power (HPLP) lab and is an associate director of the Center for Automata Processing (CAP). Prof. Stan received the Ph.D. (1996) and the M.S. (1994) degrees from UMass Amherst and the Diploma (1984) from the Politehnica University in Bucharest, Romania. Since 1996 he has been with the ECE Department at UVa, where he is now the Virginia Microelectronics Consortium (VMEC) professor. Prof. Stan was a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999. He was elected a fellow of the National Academy of Inventors (NAI) in 2026, fellow of the IEEE in 2013, received the 2024 A. Richard Newton Technical Impact Award in Electronic Design Automation (for 1995 paper "Bus-Invert Coding for Low Power I/O"), the 2018 Influential ISCA Paper Award (for 2003 paper "Temperature-aware microarchitecture"), the NSF CAREER award in 1997, and was a co-author on best paper awards at ISQED24, ASILOMAR19, LASCAS19, SELSE17, ISQED08, GLSVLSI06, ISCA03 and SHAMAN02 and IEEE Micro Top Picks in 2008 and 2003. He gave keynotes at VLSID25, iSES23, GLSVLSI23, NILES22, DCAS18, SOCC16, CogArch16, WoNDP15, iNIS15 and CNNA14. He was the chair of the VSA-TC of IEEE CAS in 2005-2007, general chair for ISLPED06 and GLSVLSI04, TPC chair for SOCC18, ISVLSI17, NanoNets07, and ISLPED05, and on technical committees for numerous conferences. He is Editor-in-Chief for the IEEE TVLSI and was Senior Editor for the IEEE TNano 2015-2022, AE for the IEEE TNano in 2012-2014, IEEE Design & Test in 2016-2022, IEEE TCAS I in 2004-2008 and for the IEEE TVLSI in 2001-2003. He was Guest Editor for the IEEE Computer special issue on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Circuits and Systems (CAS) Society in 2020-2021, 2012-2013, and 2004-2005, and for the Solid-State Circuits Society (SSCS) in 2007-2008. Prof. Stan is a fellow of the NAI and of the IEEE, a member of ACM, and Eta Kappa Nu, Phi Kappa Phi and Sigma Xi. His h-index is 60 and his i10-index is 178.

Education

M.S. ​University of Massachusetts - Amherst, 1994

Ph.D. University of Massachusetts - Amherst, 1996

​​Diploma ​Politehnica University, Bucharest, Romania, 1984

"Si jeunesse savait; Si vieillesse pouvait!" - Henri Estienne II

Research Interests

AI Hardware
Processing in Memory (PIM)
Cyber-Physical Systems (CPS)
Computational RFID
Spintronics
Nanoelectronics

Courses Taught

AI Hardware Hardware accelerators for AI
AI for Hardware Design Using AI for design of hardware

Awards

National Academy of Inventors (NAI) fellow 2025
Virginia Microelectronics Consortium (VMEC) Professor 2019
IEEE fellow 2014
NSF CAREER 1996