Xinfei Guo, Mircea R Stan. Circadian Rhythms for Future Resilient Electronic Systems LINK
Journals/Conference Papers
2020
M. Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, E. Ioana Vatajelu, Csaba Andras Moritz, Mircea R. Stan, Dan Alexandrescu and Mustafa Altun. Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance LINK
Elaheh Sadredini, Reza Rahimi, Marzieh Lenjani, Mircea R. Stan and Kevin Skadron. Impala: Algorithm/architecture co-design for in-memory multi-stride pattern matching LINK
Elaheh Sadredini, Reza Rahimi, Marzieh Lenjani, Mircea R. Stan and Kevin Skadron. FlexAmata: A universal and efficient adaption of applications to spatial automata processing accelerators LINK
Marzieh Lenjani et al.. Fulcrum: a simplified control and access mechanism toward flexible and practical in-situ accelerators LINK
Hamed Vakili et al.. Temporal Memory with Magnetic Racetracks LINK
Reza Rahimi, Elaheh Sadredini, Mircea R. Stan, and Kevin Skadron. Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAs LINK
Patricia Gonzalez-Guerrero et al.. Towards on-node Machine Learning for Ultra-low-power Sensors Using Asynchronous Σ Δ Streams LINK
Mohammad Nazmus Sakib, Hamed Vakili, Samiran Ganguly, Sergiu Mosanu, Avik W. Ghosh and Mircea Stan. Magnetic skyrmion-based programmable hardware LINK
Somayeh Rahimipour, Wameedh Nazar Flayyih, Noor Ain Kamsani, Shaiful Jahari Hashim, Mircea R. Stan and Fakhrul Zaman B. Rokhani. Low-Power, Highly Reliable Dynamic Thermal Management by Exploiting Approximate Computing LINK
Nikolaos Voros, Mircea R. Stan, Michael Huebner and Georgios Keramidas. VLSI for Next Generation CE LINK
Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Vasileios Ntinas, Orestis Liolis, Giorgos Dimitrakopoulos, Mustafa Altun, Andrew Adamatzky, Mircea R. Stan and Georgios Ch. Sirakoulis. Memristive Learning Cellular Automata: Theory and Applications LINK
2019
Chunkun Bo, Vinh Dang, Ted Xie, Jack Wadden, Mircea Stan, and Kevin Skadron. Automata Processing in Reconfigurable Architectures: In-the-Cloud Deployment, Cross-Platform Evaluation, and Fast Symbol-Only Reconfiguration. TRETS LINK
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han 0001, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Jun Zhou, Mark Zwolinski, and Stacey Weber. Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. VLSI Syst. LINK
Eric Cheng, Daniel Mueller-Gritschneder, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron, Mircea Stan, Ulf Schlichtmann, and Subhasish Mitra. Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. DAC LINK
Sergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, Lorena Anghel, and Mircea Stan. Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints. FCCM LINK
Patricia Gonzalez-Guerrero, Xinfei Guo, and Mircea R. Stan. ASC-FFT: Area-Efficient Low-Latency FFT Design Based on Asynchronous Stochastic Computing. LASCAS LINK
2018
Kevin Angstadt, Jack Wadden, Vinh Dang, Ted Xie, Dan Kramp, Westley Weimer, Mircea Stan, and Kevin Skadron. MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem. Computer Architecture Letters LINK
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, and Subhasish Mitra. Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). IEEE Trans. on CAD of Integrated Circuits and Systems LINK
Alec Roelke, and Mircea R. Stan. Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery. IEEE Trans. VLSI Syst. LINK
Mateja Putic, Swagath Venkataramani, Schuyler Eldridge, Alper Buyuktosunoglu, Pradip Bose, and Mircea Stan. Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration. DAC LINK
Yunfei Gu, Dengxue Yan, Vaibhav Verma, Mircea R. Stan, and Xuan Zhang. SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors. DAC LINK
Alec Roelke, Xinfei Guo, and Mircea Stan. OldSpot: A Pre-RTL Model for Fine-Grained Aging and Lifetime Optimization. ICCD LINK
Patricia Gonzalez-Guerrero, Xinfei Guo, and Mircea Stan. SC-SD: Towards Low Power Stochastic Computing Using Sigma Delta Streams. ICRC LINK
Samiran Ganguly, Yunfei Gu, Yunkun Xie, Mircea R. Stan, Avik W. Ghosh, and Nibir K. Dhar. Reservoir Computing Based Neural Image Filters. IECON LINK
Jack Wadden, Tommy Tracy II, Elaheh Sadredini, Lingxi Wu, Chunkun Bo, Jesse Du, Yizhou Wei, Jeffrey Udall, Matthew Wallace, Mircea Stan, and Kevin Skadron. AutomataZoo: A Modern Automata Processing Benchmark Suite. IISWC LINK
Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, and Mircea R. Stan. When "things" get older: Exploring circuit aging in IoT applications. ISQED LINK
Divya Akella Kamakshi, Xinfei Guo, Harsh N. Patel, Mircea R. Stan, and Benton H. Calhoun. A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs. ISQED LINK
Muhammed Ceylan Morgül, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, Elena Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan, and Dan Alexandrescu. Integrated Synthesis Methodology for Crossbar Arrays. NANOARCH LINK
Alec Roelke, and Mircea R. Stan. Co-Optimizing CPUs and Accelerators in Constrained Systems. SoCC LINK
Samiran Ganguly, Yunfei Gu, Mircea R. Stan, and Avik W. Ghosh. Hardware based Spatio-Temporal Neural Processing Backend for Imaging Sensors: Towards a Smart Camera. CoRR LINK
Samiran Ganguly, Yunfei Gu, Yunkun Xie, Mircea R. Stan, Avik W. Ghosh, and Nibir K. Dhar. Reservoir Computing based Neural Image Filters. CoRR LINK
2017
Xinfei Guo, and Mircea R. Stan. Implications of accelerated self-healing as a key design knob for cross-layer resilience. Integration LINK
Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, and Mircea R. Stan. Back to the Future: Digital Circuit Design in the FinFET Era. J. Low Power Electronics LINK
Mateja Putic, A. J. Varshneya, and Mircea R. Stan. Hierarchical Temporal Memory on the Automata Processor. IEEE Micro LINK
Mohamed El-Hadedy, Xinfei Guo, Martin Margala, Mircea R. Stan, and Kevin Skadron. Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems. Signal Processing Systems LINK
Mohamed El-Hadedy, Xinfei Guo, Mircea R. Stan, and Kevin Skadron. PPE-ARX: Area- and power-efficient VLIW programmable processing element for IoT crypto-systems. AHS LINK
Xinfei Guo, and Mircea R. Stan. Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery. DSN Workshops LINK
Ted Xie, Vinh Dang, Jack Wadden, Kevin Skadron, and Mircea Stan. REAPR: Reconfigurable engine for automata processing. FPL LINK
Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, and Subhasish Mitra. Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. ICCD LINK
Alec Roelke, Runjie Zhang, Kaushik Mazumdar, Ke Wang 0011, Kevin Skadron, and Mircea R. Stan. Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips. ICCD LINK
Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, and Matthew M. Ziegler. Very Low Voltage (VLV) Design. ICCD LINK
Mircea Stan. Panel discussion: Autonomy, technology, safety - Where will automotive electronics go in the next decade?. SoCC LINK
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, and Subhasish Mitra. Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). CoRR LINK
2016
Babak Falsafi, Mircea Stan, Kevin Skadron, Nuwan Jayasena, Yunji Chen, Jinhua Tao, Ravi Nair, Jaime H. Moreno, Naveen Muralimanohar, Karthikeyan Sankaralingam, and Cristian Estan. Near-Memory Data Services. IEEE Micro LINK
Runjie Zhang, Brett H. Meyer, Ke Wang 0011, Mircea R. Stan, and Kevin Skadron. Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures. IEEE Trans. VLSI Syst. LINK
Xinfei Guo, and Mircea R. Stan. Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation. ASP-DAC LINK
Ke Wang 0011, Kevin Angstadt, Chunkun Bo, Nathan Brunelle, Elaheh Sadredini, Tommy Tracy II, Jack Wadden, Mircea R. Stan, and Kevin Skadron. An overview of micron's automata processor. CODES+ISSS LINK
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, and Subhasish Mitra. Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores. DAC LINK
Jack Wadden, Nathan Brunelle, Ke Wang 0011, Mohamed El-Hadedy, Gabriel Robins, Mircea Stan, and Kevin Skadron. Generating efficient and high-quality pseudo-random behavior on Automata Processors. ICCD LINK
Jack Wadden, Vinh Dang, Nathan Brunelle, Tommy Tracy II, Deyuan Guo, Elaheh Sadredini, Ke Wang 0011, Chunkun Bo, Gabriel Robins, Mircea Stan, and Kevin Skadron. ANMLzoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures. IISWC LINK
Alec Roelke, and Mircea R. Stan. Attacking an SRAM-Based PUF through Wearout. ISVLSI LINK
Andrew Whetzel, and Mircea R. Stan. Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits. ISVLSI LINK
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, and Subhasish Mitra. CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores. CoRR LINK
2015
Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang 0011, Kevin Skadron, and Mircea R. Stan. A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC. DAC LINK
Ke Wang 0011, Yanjun Qi, Jeffrey J. Fox, Mircea R. Stan, and Kevin Skadron. Association Rule Mining with the Micron Automata Processor. IPDPS LINK
Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang 0011, Kevin Skadron, and Mircea R. Stan. Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC. ISLPED LINK
Kaushik Mazumdar, Steven Bartling, Sudhanshu Khanna, and Mircea R. Stan. A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU. ISQED LINK
Elena K. Weinberg, and Mircea R. Stan. SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range Applications. ISVLSI LINK
2014
Ke Wang 0011, Brett H. Meyer, Runjie Zhang, Kevin Skadron, and Mircea R. Stan. Walking pads: Fast power-supply pad-placement optimization. ASP-DAC LINK
Mehdi Kabir, and Mircea R. Stan. Computing with Hybrid CMOS/STO Circuits. DAC LINK
Ke Wang 0011, Brett H. Meyer, Runjie Zhang, Mircea R. Stan, and Kevin Skadron. Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization. DAC LINK
Xinfei Guo, Wayne Burleson, and Mircea R. Stan. Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques. DAC LINK
Runjie Zhang, Ke Wang 0011, Brett H. Meyer, Mircea R. Stan, and Kevin Skadron. Architecture implications of pads as a scarce resource. ISCA LINK
Yingbo Zhao, Yintang Yang, Kaushik Mazumdar, Xinfei Guo, and Mircea R. Stan. A multi-output on-chip switched-capacitor DC-DC converter for near- and sub-threshold power modes. ISCAS LINK
Mircea R. Stan, Mehdi Kabir, Stuart A. Wolf, and Jiwei Lu. Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the future. NANOARCH LINK
2013
Karthik Sankaranarayanan, Brett H. Meyer, Wei Huang 0004, Robert J. Ribando, Hossein Haj-Hariri, Mircea R. Stan, and Kevin Skadron. Architectural implications of spatial thermal filtering. Integration LINK
Vidyabhushan Mohan, Trevor Bunker, Laura M. Grupp, Sudhanva Gurumurthi, Mircea R. Stan, and Steven Swanson. Modeling Power Consumption of NAND Flash Memories Using FlashPower. IEEE Trans. on CAD of Integrated Circuits and Systems LINK
Mircea Stan. Breaking power delivery walls using voltage stacking. ISVLSI LINK
Mircea R. Stan, Mehdi Kabir, Jiwei Lu, and Stuart A. Wolf. Nano-pattemed coupled spin torque nano oscillator (STNO) arrays - A potentially disruptive multipurpose nanotechnology. NEWCAS LINK
2012
Stuart N. Wooters, Adam C. Cabe, Zhenyu Qi, Jiajing Wang, Randy W. Mann, Benton H. Calhoun, Mircea R. Stan, and Travis N. Blalock. Tracking On-Chip Age Using Distributed, Embedded Sensors. IEEE Trans. VLSI Syst. LINK
Kaushik Mazumdar, and Mircea R. Stan. Breaking the 3D IC power delivery wall. ACSCC LINK
Kaushik Mazumdar, and Mircea R. Stan. Breaking the power delivery wall using voltage stacking. ACM Great Lakes Symposium on VLSI LINK
Stevo D. Bailey, and Mircea R. Stan. A new taxonomy for reconfigurable prefix adders. ISCAS LINK
Mircea R. Stan, Mehdi Kabir, Jiwei Lu, and Stuart A. Wolf. Self-assembled multiferroic magnetic QCA structures for low power systems. ISCAS LINK
Mehdi Sadi, and Mircea Stan. Design of near threshold All Digital Delay Locked Loops. SoCC LINK
Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, and Brett H. Meyer. ArchFP: Rapid prototyping of pre-RTL floorplans. VLSI-SoC LINK
2011
Wei Huang, Malcolm Allen-Ware, John B. Carter, Mircea R. Stan, and Edmund Cheng. Temperature-Aware Architecture: Lessons and Opportunities. IEEE Micro LINK
Wei Huang 0004, Karthick Rajamani, Mircea R. Stan, and Kevin Skadron. Scaling with Design Constraints: Predicting the Future of Big Chips. IEEE Micro LINK
Mehdi Kabir, Mircea R. Stan, Stuart A. Wolf, Ryan B. Comes, and Jiwei Lu. RAMA: a self-assembled multiferroic magnetic QCA for low power systems. ACM Great Lakes Symposium on VLSI LINK
Adam C. Cabe, and Mircea R. Stan. Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM. ACM Great Lakes Symposium on VLSI LINK
Clinton Wills Smullen IV, Vidyabhushan Mohan, Anurag Nigam, Sudhanva Gurumurthi, and Mircea R. Stan. Relaxing non-volatility for fast and energy-efficient STT-RAM caches. HPCA LINK
Clinton Wills Smullen IV, Anurag Nigam, Sudhanva Gurumurthi, and Mircea R. Stan. The STeTSiMS STT-RAM simulation and modeling system. ICCAD LINK
Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, and Mircea R. Stan. Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM). ISLPED LINK
Taniya Siddiqua, Sudhanva Gurumurthi, and Mircea R. Stan. Modeling and analyzing NBTI in the presence of Process Variation. ISQED LINK
2010
Stuart A. Wolf, Jiwei Lu, Mircea R. Stan, Eugene Chen, and Daryl M. Treger. The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory. Proceedings of the IEEE LINK
Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, and Benton H. Calhoun. Improving SRAM Vmin and yield by using variation-aware BTI stress. CICC LINK
Adam C. Cabe, Zhenyu Qi, and Mircea R. Stan. Stacking SRAM banks for ultra low power standby mode operation. DAC LINK
Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, and Mircea R. Stan. SRAM-based NBTI/PBTI sensor system design. DAC LINK
Vidyabhushan Mohan, Sudhanva Gurumurthi, and Mircea R. Stan. FlashPower: A detailed power model for NAND flash memory. DATE LINK
Mircea Stan. Reliability/wearout-aware design. Green Computing Conference LINK
Vidyabhushan Mohan, Taniya Siddiqua, Sudhanva Gurumurthi, and Mircea R. Stan. How I Learned to Stop Worrying and Love Flash Endurance. HotStorage LINK
Zhenyu Qi, Brett H. Meyer, Wei Huang 0004, Robert J. Ribando, Kevin Skadron, and Mircea R. Stan. Temperature-to-power mapping. ICCD LINK
2009
Sudhanva Gurumurthi, Sriram Sankar, and Mircea R. Stan. Using Intradisk Parallelism to Build Energy-Efficient Storage Systems. IEEE Micro LINK
Sriram Sankar, Yan Zhang 0028, Sudhanva Gurumurthi, and Mircea R. Stan. Sensitivity-Based Optimization of Disk Architecture. IEEE Trans. Computers LINK
Mircea R. Stan, Dincer Unluer, Avik W. Ghosh, and Frank Tseng. Graphene Devices, Interconnect and Circuits - Challenges and Opportunities. ISCAS LINK
Wei Huang 0004, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, and Mircea R. Stan. Differentiating the roles of IR measurement and simulation for power and temperature-aware design. ISPASS LINK
Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, and Mircea R. Stan. Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. ISQED LINK
2008
Wei Huang 0004, Karthik Sankaranarayanan, Kevin Skadron, Robert J. Ribando, and Mircea R. Stan. Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model. IEEE Trans. Computers LINK
Wei Huang 0004, Mircea R. Stan, Karthik Sankaranarayanan, Robert J. Ribando, and Kevin Skadron. Many-core design from a thermal perspective. DAC LINK
Zhenyu Qi, and Mircea R. Stan. NBTI resilient circuits using adaptive body biasing. ACM Great Lakes Symposium on VLSI LINK
Sriram Sankar, Sudhanva Gurumurthi, and Mircea R. Stan. Intra-disk Parallelism: An Idea Whose Time Has Come. ISCA LINK
Sriram Sankar, Sudhanva Gurumurthi, and Mircea R. Stan. Sensitivity Based Power Management of Enterprise Storage Systems. MASCOTS 2007
Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, and Mircea R. Stan. Designing CMOS/molecular memories while considering device parameter variations. JETC LINK
Alain E. Kaloyeros, Mircea R. Stan, Barry Arkles, Robert E. Geer, Eric T. Eisenbraun, James E. Raynolds, Anand Gadre, Yongqiang Xue, and James Ryan. Conformational Molecular Switches for Post-CMOS Nanoelectronics. IEEE Trans. on Circuits and Systems LINK
Garrett S. Rose, and Mircea R. Stan. A Programmable Majority Logic Array Using Molecular Scale Electronics. IEEE Trans. on Circuits and Systems LINK
Zhijian Lu, Wei Huang 0004, Mircea R. Stan, Kevin Skadron, and John Lach. Interconnect Lifetime Prediction for Reliability-Aware Systems. IEEE Trans. VLSI Syst. LINK
Yan Zhang 0028, Sudhanva Gurumurthi, and Mircea R. Stan. SODA: Sensitivity Based Optimization of Disk Architecture. DAC LINK
Yan Zhang 0028, and Mircea R. Stan. Temperature-aware circuit design using adaptive body biasing. ACM Great Lakes Symposium on VLSI LINK
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, and Mircea R. Stan. Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI LINK
Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, and Mircea R. Stan. Multi-Dimensional Circuit and Micro-Architecture Level Optimization. ISQED LINK
Zhenyu Qi, and Mircea R. Stan. Accurate Back-of-the-Envelope Transistor Model for Deep Sub-micron MOS. MSE LINK
Mircea R. Stan, Adam C. Cabe, Sudeep Ghosh, and Zhenyu Qi. Teaching Top-Down ASIC/SoC Design vs Bottom-Up Custom VLSI. MSE LINK
2006
Wei Huang 0004, Shougata Ghosh, Sivakumar Velusamy, Karthik Sankaranarayanan, Kevin Skadron, and Mircea R. Stan. HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design. IEEE Trans. VLSI Syst. LINK
Zhijian Lu, Yan Zhang 0028, Mircea R. Stan, John Lach, and Kevin Skadron. Procrastinating voltage scheduling with discrete frequency sets. DATE LINK
Garrett S. Rose, and Mircea R. Stan. A programmable majority logic array using molecular scale electronics. FPGA LINK
Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, and James M. Tour. Design approaches for hybrid CMOS/molecular memory based on experimental device data. ACM Great Lakes Symposium on VLSI LINK
Zhenyu Qi, Wei Huang, Adam C. Cabe, Wenqian Wu, Yan Zhang 0028, Garrett S. Rose, and Mircea R. Stan. A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors. SoCC LINK
Mircea R. Stan, Garrett S. Rose, and Matthew M. Ziegler. Hybrid CMOS/Molecular Electronic Circuits. VLSI Design LINK
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006. 2005
Karthik Sankaranarayanan, Sivakumar Velusamy, Mircea R. Stan, and Kevin Skadron. A Case for Thermal-Aware Floorplanning at the Microarchitectural Level. J. Instruction-Level Parallelism LINK
Zhijian Lu, John Lach, Mircea R. Stan, and Kevin Skadron. Improved Thermal Management with Reliability Banking. IEEE Micro LINK
Yan Zhang 0028, Zhijian Lu, John Lach, Kevin Skadron, and Mircea R. Stan. Optimal procrastinating voltage scheduling for hard real-time systems. DAC LINK
Sivakumar Velusamy, Wei Huang 0004, John Lach, Mircea R. Stan, and Kevin Skadron. Monitoring Temperature in FPGA based SoCs. ICCD LINK
Yan Zhang 0028, Travis N. Blalock, and Mircea R. Stan. A three-level toggle-avoid bus signaling scheme. ISCAS (2) LINK
Wei Huang 0004, Eric Humenay, Kevin Skadron, and Mircea R. Stan. The need for a full-chip and package thermal model for thermally optimized IC designs. ISLPED LINK
2004
Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang 0004, Sivakumar Velusamy, and David Tarjan. Temperature-aware microarchitecture: Modeling and implementation. TACO LINK
Dharmesh Parikh, Kevin Skadron, Yan Zhang 0028, and Mircea R. Stan. Power-Aware Branch Prediction: Characterization and Design. IEEE Trans. Computers LINK
Garrett S. Rose, Matthew M. Ziegler, and Mircea R. Stan. Large-signal two-terminal device model for nanoelectronic circuit analysis. IEEE Trans. VLSI Syst. LINK
Lei He, Weiping Liao, and Mircea R. Stan. System level leakage reduction considering the interdependence of temperature and leakage. DAC LINK
Wei Huang 0004, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, and Sivakumar Velusamy. Compact thermal modeling for temperature-aware design. DAC LINK
Yingmin Li, Dharmesh Parikh, Yan Zhang 0028, Karthik Sankaranarayanan, Mircea R. Stan, and Kevin Skadron. State-Preserving vs. Non-State-Preserving Leakage Control in Caches. DATE LINK
Matthew M. Ziegler, and Mircea R. Stan. A Unified Design Space for Regular Parallel Prefix Adders. DATE LINK
Zhijian Lu, Wei Huang 0004, John Lach, Mircea R. Stan, and Kevin Skadron. Interconnect lifetime prediction under dynamic stress for reliability-aware design. ICCAD LINK
Mircea R. Stan. Systolic counters with unique zero state. ISCAS (2) Mircea R. Stan, and Yan Zhang 0028. Perfect 3-Limited-Weight Code for Low Power I/O. PATMOS LINK
Mircea R. Stan, Fatih Hamzaoglu, and David Garrett. Non-Manhattan maze routing. SBCCI LINK
2003
Mircea R. Stan, and Kevin Skadron. Guest Editors' Introduction: Power-Aware Computing. IEEE Computer LINK
Zhijian Lu, John Lach, Mircea R. Stan, and Kevin Skadron. Alloyed Branch History: Combining Global and Local Branch History for Robust Performance. International Journal of Parallel Programming LINK
Kevin Skadron, Mircea R. Stan, Wei Huang 0004, Sivakumar Velusamy, Karthik Sankaranarayanan, and David Tarjan. Temperature-Aware Computer Systems: Opportunities and Challenges. IEEE Micro LINK
Mircea R. Stan, Kevin Skadron, Marco Barcella, Wei Huang 0004, Karthik Sankaranarayanan, and Sivakumar Velusamy. HotSpot: a dynamic compact thermal model at the processor-architecture level. Microelectronics Journal LINK
Zhijian Lu, John Lach, Mircea R. Stan, and Kevin Skadron. Reducing Multimedia Decode Power using Feedback Control. ICCD LINK
Kevin Skadron, Mircea R. Stan, Wei Huang 0004, Sivakumar Velusamy, Karthik Sankaranarayanan, and David Tarjan. Temperature-Aware Microarchitecture. ISCA LINK
Mircea R. Stan, and Marco Barcella. MTCMOS with outer feedback (MTOF) flip-flops. ISCAS (5) LINK
Matthew M. Ziegler, and Mircea R. Stan. The CMOS/nano interface from a circuits perspective. ISCAS (4) LINK
2002
Mircea R. Stan. CMOS Circuits with Subvolt Supply Voltages. IEEE Design & Test of Computers LINK
Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea R. Stan, and Vivek De. None IEEE Trans. VLSI Syst. LINK
Zhijian Lu, Jason Hein, Marty Humphrey, Mircea R. Stan, John Lach, and Kevin Skadron. Control-theoretic dynamic frequency and voltage scaling for multimedia workloads. CASES LINK
Mircea R. Stan, and Avishek Panigrahi. The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits. DATE LINK
Kevin Skadron, Tarek F. Abdelzaher, and Mircea R. Stan. Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management. HPCA LINK
Dharmesh Parikh, Kevin Skadron, Yan Zhang 0028, Marco Barcella, and Mircea R. Stan. Power Issues Related to Branch Prediction. HPCA LINK
Matthew M. Ziegler, and Mircea R. Stan. A Case for CMOS/nano co-design. ICCAD LINK
Fatih Hamzaoglu, and Mircea R. Stan. Circuit-level techniques to control gate leakage for sub-100nm CMOS. ISLPED LINK
Yan Zhang 0028, John Lach, Kevin Skadron, and Mircea R. Stan. Odd/even bus invert with two-phase transfer for buses with coupling. ISLPED LINK
Mircea R. Stan, and Kevin Skadron. Teaching processor architecture with a VLSI perspective. WCAE LINK
2001
Mircea R. Stan. Low-power CMOS with subvolt supply voltages. IEEE Trans. VLSI Syst. LINK
Alvar Dean, David Garrett, Mircea R. Stan, and Sebastian Ventrone. Low Power Design for ASIC Cores. VLSI Design LINK
David Garrett, and Mircea R. Stan. A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications. ISCAS (4) LINK
Joshua L. Garrett, and Mircea R. Stan. Active threshold compensation circuit for improved performance in cooled CMOS systems. ISCAS (4) LINK
Matthew M. Ziegler, and Mircea Stan. Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product. ISCAS (2) LINK
1999
David Garrett, Mircea R. Stan, and Alvar Dean. Challenges in clockgating for a low power ASIC methodology. ISLPED LINK
Mircea R. Stan. Optimal Voltages and Sizing for Low Power. VLSI Design LINK
1998
Mircea R. Stan, Alexandre F. Tenca, and Milos D. Ercegovac. Long and Fast Up/Down Counters. IEEE Trans. Computers LINK
Mircea R. Stan. Low threshold CMOS circuits with low standby current. ISLPED LINK
David Garrett, and Mircea R. Stan. Low power architecture of the soft-output Viterbi algorithm. ISLPED LINK
1997
Mircea R. Stan, and Wayne P. Burleson. Low-power encodings for global communication in CMOS VLSI. IEEE Trans. VLSI Syst. LINK
Mircea R. Stan. Synchronous Up/Down Counter with Clock Period Independent of Counter Size. IEEE Symposium on Computer Arithmetic LINK
David Garrett, and Mircea R. Stan. Power reduction techniques for a spread spectrum based correlator. ISLPED LINK
1996
Mircea R. Stan, and Wayne P. Burleson. Two dimensional codes for low power. ISLPED LINK
1995
Mircea R. Stan, and Wayne P. Burleson. Bus-invert coding for low-power I/O. IEEE Trans. VLSI Syst. LINK
Mircea R. Stan, and Wayne P. Burleson. Coding a terminated bus for low power. Great Lakes Symposium on VLSI LINK
1994
Mircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, and Roderic A. Grupen. Analog VLSI for robot path planning. VLSI Signal Processing LINK