Robust Low Power VLSI

Our Group

The Robust Low Power VLSI Group, led by Professor Ben Calhoun, investigates research topics related to modern VLSI design. 

Calhoun group photo RLP VLSI research group

Among the many challenges facing circuit designers in deep sub-micron technologies, power and variation are perhaps the most critical. Our group's focus is to confront these problems in a range of applications and different regions of the design space.

Our Research

Our research interests include low power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation tolerant circuit design methodologies, and medical applications for low energy electronics.

  • An E-textile with integrated silicon chip and embroidered conductive wire yarns

    E-textiles

    Electronic Textiles (E-Textiles) integrate electronic circuits into textile substrates for applications such as smart wearables. Our work in this area focuses on innovating silicon-level electronics for computing, communication, and power management to enable ultra-compact and unobtrusive form factors.

  • An ultra energy-efficient on-chip clock design using a duty-cycled digital frequency-locked loop

    Energy Efficient Circuit Design

    Our research in energy-efficient design focuses on new architectural techniques and circuit-level innovations to reduce power consumption in integrated circuits and do more work with less energy.

  • A 6.45uW highly-integrated SoC (System-on-Chip) for wireless health monitoring

    System-on-Chips (SoCs)

    System-on-Chip (SoC) combines broad functionality onto a single silicon chip to enable compact and efficient operation in either general use-cases in the Internet-of-Things (IoT) or specific applications such as health sensing.