Chip Gallery

65nm LP, 2026

This chip validates derived analytical models on DLS logic, presenting measurements several unique DLS standard cell libraries with traditional CMOS logic included for comparison. Measurement results demonstrate a minimum DLS leakage power of 0.26 fW per inverter at 0.35 V, over 350x lower than CMOS inverters at the same supply voltage. At 1.2 V, this leakage reduction increases to >1000x. Synthesized 8-bit DLS multiply-accumulate (MAC) circuits are also demonstrated for validation.

Designer(s): Daniel, Jacob

180nm BCD, 2025

To reduce size for 5W flyback converters, we propose a highly integrated ACF controller that can adaptively operate from 300kHz to over 500kHz switching frequency with ZVS and an 85μH (Lm) transformer. Our PSR control IC reduces the number of off-chip components for the full AC-DC system, achieving a 4 99cm^3 volume and a power density of 1.0W/cm^3 at 5V/1A from 85-265Vac input with a peak efficiency of 81.0%.

Designer(s): Aki, Shan, Xinjian, Omar, Nugaira, Daniel

65nm CMOS, 2025

our paper presents a comparison of various on-chip PV cell configurations, implemented using a 0.6mm x 0.6mm test chip realized in 65nm deep-nwell (DNW) CMOS technology. The experimental results demonstrate that, depending on diode arrangements, separate configurations achieve a maximum open-circuit voltage of 0.54V and a peak power density of 1.18 µW/mm2 at 20 klux illumination.

Designer(s): Anjali, Xinjian

65nm CMOS, 2025

We propose a sub-μwatt digital temperature compensation architecture that generates voltage and current references with a user-defined temperature response rather than a fixed, near-ideal response. This flexible approach allows a single programmable design to be reused easily to produce different profiles over temperature, reducing design time.

Designer(s): Natalie, Prerana, Suprio

65nm CMOS, 2025

This paper presents a 0.36-mm2 I2C-to-SPI converter chip designed for electronic textile (E-textile) applications, featuring an on-the-fly conversion scheme that eliminates the need for on-chip data buffers and internal clock generation. By leveraging the synchronous nature of both I2C and SPI protocols, the proposed design forwards each incoming I2C data bit, SDA (Serial Data Line) directly to the SPI output using the I2C serial clock line (SCL), thereby reducing both area and power consumption.

Designer(s): Omar, Zhenghong, Suprio, Fahim, Samit

65nm CMOS, 2025

A cooperative fully on-chip switched-capacitor voltage regulator (SCVR) in 65 nm CMOS implements a communication-free distributed power delivery system for Networks-on-Textiles (kNOTs). The design enables multiple chips to act in parallel to scale output current and improve load regulation.

Designer(s): Aki, Shan

65nm CMOS, 2025

This article presents kNOT, a scalable, distributed, and 2-D Network-On-Textile (kNOT) comprising miniaturized systems on chip (SoCs) and bypass SPI (bySPI) networking chiplets that together enable diverse networking and computational tasks.

Designer(s): Anjali, Zhenhong, Braden, Jinhua, Aki, Fahim, Charlie

65nm CMOS, 2024

This fully autonomous triple-input hybrid inductor-capacitor multi-output (TIHICMO) EHPMU that can harvest energy from dual input sources, regulate three custom output rails, adaptively switch among multi-conversion methods, cold startup (CS) from all the inputs/outputs, and enable energy recycling and sharing among multiple rails. This EHPMU achieves a 5.8nA quiescent current, a wide dynamic range of 8.8x104 , a peak efficiency of 90.1%

Designer(s): X. Liu, A. Agrawal, A. Tanaka, B.H. Calhoun

65nm CMOS, 2024

This 10-channel reconfigurable capacitance-to-digital converter (CDC) enables sub-μW wearable sensing applications. The proposed multichannel architecture supports 10 channels with a shared reconfigurable 6-bit differential analog-to-digital converter (ADC). The reconfigurable nature of the CDC enables adaptive sensing range and sensing speed based on the target application.

Designer(s): O. Faruqe, D. Lee, N.B. Ownby, B.H. Calhoun

65nm CMOS, 2023

This work presents an ULP “bypass-SPI” chip-to-chip interconnect bus designed specifically for fabric-based network communication, requiring only a fixed set of four wires. This interconnect bus allows the chips to bypass the interconnect signals to the downstream chips using a dedicated bypass procedure, facilitating small form factors. A voltage and direction controller is integrated on-chip, which allows the expansion of interconnect signals in multiple directions, supporting mesh-style distributed fiber networks and enabling voltage shifting

Designer(s): X. Liu, Z. Chen, N.G. Mim, A. Agrawal, and B.H. Calhoun

65nm CMOS, 2023

A 2.4GHz binary frequency-shift keying (BFSK) heterodyne WuRx with low-power All-Digital Phase Locked Loop (ADPLL) and sharp intermediate frequency (IF) filtering. It achieves -102dBm sensitivity with 2.2µA to 171µA power range at 16s to 100ms latency. It demonstrates a -27/-30dB continuous wave (CW) signal to interference ratio (SIR) at 3/5MHz offset from the carrier.

Designer(s): L. Zhang, D. Duvvuri, S. Bhattacharya, A. Dissanayake, X. Liu, H.L. Bishop, Y. Zhang, T.N. Blalock, B.H. Calhoun, and S.M. Bowers

65nm CMOS, 2023

This fully autonomous system-onchip (SoC) can be distributed along a fiber strand, capable of simultaneously harvesting energy, cooperatively scaling performance, sharing power, and booting-up with other in-fiber SoCs for ultra-low-power (ULP) sensing applications. The SoC achieves 33 nW power consumption for the whole chip under 92 Lux lighting condition and can reduce control power down to 2.7 nW for the EHPMU. With the proposed power sharing and cooperative DVFS techniques, the SoC reduces the illuminance needed to stay alive by >7× down to 12 Lux

Designer(s): X. Liu, D.S. Truesdell, O. Faruqe, L. Parameswaran, M. Rickley, A. Kopanski, L. Cantley, A. Coon, M. Bernasconi, T. Wang , and B.H. Calhoun

65nm CMOS, 2022

This work presents NanoWattch, a self-powered SoC in 65-nm CMOS with integrated temperature sensing for miniaturized IoT applications. NanoWattch can cold-start and sustain operation directly from ambient light with a photovoltaic input as low as 160mV. A performance-scalable RISC-V processor with 6kB SRAM and DVFS subsystem enable system power consumption to continuously adapt to ambient energy conditions down to a minimum total system power of 3nW to provide always-on operation in a mm-scale form factor.

Designer(s): Daniel, Xinjian, Jacob, Shourya, Shuo

65nm CMOS, 2022

This work demonstrates a sub-nW-quiescent, high-efficiency buck converter with fast DVFS, fast load-transient response, and a six-order dynamic range for ULP IoT SoCs. Using an asynchronous control scheme, adaptive dead-time controller, and length-split + SuWd-optimized power stage, it achieves robust, efficient power delivery across PVT. The design is fully self-contained with on-chip bias generator, clock, and PoR. Fabricated in 65 nm, it delivers 802 pW quiescent power, 93% peak efficiency, 0.5–2.75 mW range, 56 mV droop for 45 nA→1 mA steps, and 10–20 µs DVFS tracking, enabling energy-minimal operation in ULP IoT systems.

Designer(s): Xinjian

65nm CMOS, 2022

A self-powered IoT SoC must operate in the sub-µW regime while dynamically balancing ultra-low power, performance, energy-harvester size, and lifetime. MEPT techniques extend lifetime but often require frequent voltage comparisons, high-frequency clocks, or specialized body-biasing, leading to higher power and limited efficiency. To meet ULP IoT requirements such as ultra-low quiescent power, high-efficiency delivery, scalable performance, and energy minimization; we propose an IoT SoC with a triple-mode PMU that unifies energy-performance scaling, event-driven fast DVFS, and MEPT. The system achieves 194 nW minimum SoC power, 5.2 nW PMU quiescent power, 92.6% peak efficiency, and >10⁴ dynamic range. The PMU transitions among energy-aware, performance-aware, and MEPT modes based on event priority and available harvested energy, enabling continuous optimization of energy usage and performance.

Designer(s): Xinjian, Sumanth, Jacob

65nm CMOS, 2022

Energy-harvesting PMUs (EHPMUs) are increasingly essential for self-powered IoT systems, providing ambient-energy extraction and load powering within a single block. Among existing architectures, multi-input single-inductor multi-output (MISIMO) designs offer small form factor, high efficiency, multi-modal energy extraction, and the ability to serve diverse loads. However, prior EHPMUs suffer from high quiescent power, limited dynamic range, two-stage power delivery with cascaded losses and missing on-chip components such as voltage references needed for full deployment. This work introduces a fully autonomous MISIMO EHPMU platform that harvests from three AC/DC modalities, generates four custom voltage rails, and integrates on-chip MPPT and multi-modal cold start. The proposed system achieves 32 nA quiescent current, a 1.2×10⁵ dynamic range, 3.2× energy-extraction gain for piezo harvesting, and 80% efficiency at a 1-µA load, meeting the stringent requirements of self-powered IoT applications.

Designer(s): Shuo, Xinjian

65nm CMOS, 2021

A 2.4-GHz wake-up receiver (WuRX) achieving 91.5 dBm sensitivity with a state-of-the-art power and latency combination of 2 at 100 ms. The proposed within-packet duty-cycling method employs a carrier-sense mechanism to turn off the WuRX early under idle channel conditions, which reduces the dc-power compared with conventional asynchronous packet-level duty cycling

Designer(s): Anjana, Henry

65nm CMOS, 2021

MemGen (“Memory Macro Generator”) is an open-source memory macro generation framework that creates tapeout-ready integrated memories across a broad range of voltages, frequencies, and capacities by using a template and cell-based design methodology and leveraging the conventional digital tool flow to generate optimized memories based on high-level user intent, making it highly modular, process-portable, and easily augmentable

Designer(s): Sumanth, Shourya

65nm CMOS, 2021

Tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO2, and pulse transit time, which is a critical intermediate parameter to derive blood pressure.

65nm CMOS, 2021

An on-chip oscillator for energy-efficient Internet-of-Things (IoT) applications based on a duty-cycled digital frequency-locked loop (DFLL) that reduces energy by disabling energy-hungry components and only periodically reactivating them to keep the output frequency stabilized during temperature drifts.

Designer(s): Daniel, Shuo

65nm CMOS, 2020

A -108dBm sensitivity, 430MHz, 130nW-41μW, 6.25bps-4.2kbps, digitally tunable wake-up and data receiver in 65nm CMOS employing 2-tone RF OOK modulation and an AlN MEMS resonator, the receiver attains close-in SIR of -25dB at 0.12% and far-out SIR of -28dB at 0.7% frequency offset from the carrier. Digitally configurable dynamic ranges of 11dB, 410X, 672X are achieved for sensitivity, power, and latency, respectively. The design receives data at a 4.2kbps bit-rate at - 108dBm sensitivity while consuming 41μW

Designer(s): Anjana, Jesse, Henry B., Daniel, Henry M.

65nm CMOS, 2020

An ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs).

Designer(s): Shuo, Jacob, Sumanth

65nm CMOS, 2020

A 16kb SRAM that achieves an ultra-low leakage of less than 132pW across its entire operational VDD range (0.3-0.9V). It is implemented using a new robust two-port bitcell with 614aW leakage, which is the lowest leakage bitcell reported to date.

Designer(s): Shourya, Daniel

65nm CMOS, 2019

An energy-optimized and highly temperature-stable FLL design in 65-nm CMOS that achieves 20.3-ppm/°C temperature stability from -20 °C to 60 °C and an energy efficiency of 44.6-fJ/cycle at 23 °C (45.3 nW at 1.016 MHz), which is the highest energy efficiency reported to date for a fully on-chip oscillator, regardless of architecture, operating frequency, or temperature stability

Designer(s): Daniel, Anjana

65nm CMOS, 2019

A RISC-V microprocessor implemented using a proposed scalable dynamic leakage suppression (SDLS) logic style. Together with a custom adaptive clock generator and voltage scaling controller, the SDLS RISC-V microprocessor realizes a fully integrated modified dynamic voltage and frequency scaling (DVFS) scheme that enables nW-level performance flexibility for battery-less IoT sensing nodes in energy-scarce environments.

Designer(s): Daniel, Jacob, Sumanth, Ningxi

130nm CMOS, 2019

This work presents an integrated maximum-power-point tracking (MPPT) algorithm and its implementation for the high-performance parallel-synchronized-switch harvesting-on-inductor (SSHI) rectifier, which uses the Perturb and Observe (P&O) method and a proposed power monitor for output power evaluation

Designer(s): Shuo, Abhishek

65nm CMOS, 2019

An on-chip RC relaxation oscillator (ROSC) with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0-40°C.

Designer(s): Ningxi, Rishika, Anjana, Daniel, Sumanth

65nm CMOS, 2019

A 640 pW, 22 pJ/conversion gate leakage-powered temperature sensor with 0.25°C resolution and -2.7/1.8°C worst-case inaccuracy from - 20 °C to 100°C. Gate leakage currents drive both the sensing and sampling elements to provide compact but reliable operation that balances low power and low energy for flexible application use

Designer(s): Daniel

65nm CMOS, 2019

Achieves the lowest current consumption, the highest current efficiency, the largest dynamic load range, the lowest load current, and the smallest output voltage ripple amongst state-of-the-art DLDOs

Designer(s): Shuo

130nm CMOS, 2017

An ultra-low-power differential wireline transceiver in 130 nm CMOS to solve the communication power bottleneck in on-body sensor networks where individual sensor nodes operate below 10 µW. The work targets low data-rate health and fitness applications and demonstrates reliable multi-meter links over both 3m Ethernet cable and flexible textile interconnects with negligible active and sleep power.

Designer(s): Christopher Lukas, Benton Calhoun, Raj Bhakta, Jesse Jur

130nm CMOS, 2017

A closed loop self-tuning 256kb 6T SRAM with 0.38V-1.2V extended operating range using combined read and write assists and canary-based VMIN tracking is presented. 337X and 4.3X power reductions are achieved using multiple assists and VMIN tracking, respectively; combining both saves 1444X in active power and 12.4X in leakage at the 0.38V.

Designer(s): Arijit Banerjee, Ningxi Liu, Harsh N. Patel, Benton H. Calhoun, John Poulton and C. Thomas Gray

130nm CMOS, 2017

An ultra-low-power differential wireline transceiver in 130 nm CMOS for on-body sensor networks. The chip targets sub‑kHz data rates over multi‑meter links while keeping both active and sleep power in the nW/pW range.​ The transmitter uses complementary NMOS/PMOS source followers in a class‑B‑like structure to generate a reduced-swing, VDD/2‑centered differential signal without static bias current, eliminating traditional analog drivers and resistive loads. The receiver combines a subthreshold continuous-time clock comparator with a stacked-NMOS bias generator for 0.24–1.0 V operation and a clocked data comparator plus contention-free SR latch to minimize leakage while retaining data at deep‑subthreshold voltages.

Designer(s): Abhishek Roy, Benton H. Calhoun

130nm CMOS, 2017

This paper presents a near/subthreshold FPGA with low-swing global interconnect, folded switch box (SB), per-path voltage scaling, and power-gating. A fully programmable 512-look-up-table FPGA chip is fabricated in 130nm CMOS. When implementing a 4bit-adder, the measured energy of the proposed FPGA is 15% less than the normalized energy of the state-of-the-art. When implementing fifteen selected low-power applications, the estimated energy of the proposed FPGA is on average 75x lower than Microsemi IGLOO. 

Designer(s): He Qi, Oluseyi Ayorinde, and Benton H. Calhoun

130nm CMOS, 2017

This paper presents a lossless sensor data compression accelerator for power reduction in wireless body sensors. First, a low complexity compression algorithm is demonstrated for the first time on electrocardiogram (ECG) and acceleration sensor data. Second, the algorithm is implemented as a custom hardware accelerator on a health monitoring driven System on Chip (SoC) in a 130 nm process. The accelerator is closely integrated with the transmitter interface to minimize its contribution to system power and reduce user overhead. The accelerator adds only 4.4 nW processing overhead and reduces the required transmitter duty cycle by 3.7x, reducing the system power by 2.9x, and allowing the entire system to consume just 2.62 μW when transmitting ECG data at a 360 Hz sampling rate.

Designer(s): Jacob Breiholz, Farah Yahya, Christopher Lukas, Xing Chen, Kevin Leach, David Wentzloff, and Benton Calhoun

130nm CMOS, 2017

A closed loop self-tuning 256kb 6T SRAM with 0.38V-1.2V extended operating range using combined read and write assists and canary-based VMIN tracking is presented. 337X and 4.3X power reductions are achieved using multiple assists and VMIN tracking, respectively; combining both saves 1444X in active power and 12.4X in leakage at the 0.38V.

Designer(s): Arijit Banerjee; Ningxi Liu; Harsh N. Patel; Benton H. Calhoun; John Poulton; C. Thomas Gray

90nm FDSOI, 2016

an implementation of a 16-bit MSP430 processor for ultra-low-power (ULP) systems catering to battery-less wireless sensor nodes, biomedical, and other IoT applications. Implemented in a custom extremely low power (xLP) 90nm FDSOI process, executing a peak detection algorithm at 250 kHz. It supports the standard MSP430 instruction set architecture (ISA) and demonstrates QRS peak detection for an Electrocardiogram (ECG) application.

Designer(s): Abhishek Roym Peter J. Grossmann, Steven A. Vitale

130nm CMOS, 2016

an ultra-low power crystal (XTAL) oscillator circuit for generating a 32.768 kHz clock source for real-time clock generation. An inverting amplifier operational from 0.3 V VDD oscillates the XTAL resonator and achieves a power consumption of 2.1 nW. A duty-cycling technique powers down the XTAL amplifier without losing the oscillation and reduces the power consumption to 1.5 nW

Designer(s): Aatmesh Shrivastava, Divya Akella Kamakshi

130nm CMOS, 2016

a fully on-chip clock-source system in which an ultra-low-power diode-based temperature-uncompensated oscillator (OSCdiode) serves as the main clock source and frequency locks to a higher-power temperature-compensated oscillator (OSCcmp) that is disabled after each locking event to save power. The locking allows the stability of the uncompensated oscillator to stay within the stability bound of the compensated design.

Designer(s): Dibya Akella Kamakshi, Aatmesh Shrivastava, Chuhong Duan

55nm CMOS, 2016

an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (VT) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the technology to maximize the energy/power saving.

Designer(s): Harsh N. Patel, Abhishek Roy, Farah B. Yahya, Ningxi Liu

130nm CMOS, 2016

presents an ultra-low swing level converter with integrated charge pumps that shows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-V output. Lowering the input allowable for a single-ended level converter supports energy harvesting systems that need to use very low voltages.

Designer(s): Yu Huang, Aatmesh Shrivastava, Laura E. Barnes

130nm CMOS, 2016

compares the impact of power supply variation on the performance of register-based and latch-based digital circuits. A 32-tap, 16-bit FIR filter is fabricated using both flip-flops and latches in a 130nm CMOS process

Designer(s): Abhishek Roy

130nm CMOS, 2016

A 1 KB SRAM macro for Internet of Things using 8T high-threshold (high-VT) static random access memory (SRAM) cells with word line boosting to eliminate write failures coupled with a read-before-write scheme to address read-disturb in half-selected cells. Due to the reduced on current in high-VT devices, read word line boosting is implemented to improve the drive strength of the read buffer, and to eliminate read failures. Leakage currents through the unselected cells during a read operation is addressed by boosting the footer virtual VSS (VVSS) of the read port to the supply voltage (VDD)

Designer(s): Farah B. Yahya, Harsh N. Patel, James Boley, Arijit Banerjee

130nm CMOS, 2015

This 130-nm test chip implements fifteen hardware architectures for base-two logarithmic approximation, spanning Mitchell’s algorithm, piecewise-linear and quadratic error-compensated designs, and direct approximations. The chip integrates optimized segment-based compensation using Hamming-weight minimization and slope-pattern recognition, and includes a new quadratic compensation scheme with near-zero average error.

Designer(s): Alicia Klinefelter; Joseph Ryan; James Tschanz; Benton H. Calhoun

130nm CMOS, 2015

This 130-nm prototype chip implements an optimized chip-to-chip communication link tailored for energy-constrained systems. By jointly considering energy-per-cycle and energy-per-bit, the design identifies the most efficient operating voltage and activity factor, minimizing wasted power across diverse use cases. Silicon measurements demonstrate ultra-low-power operation, achieving 0.38 pJ/bit energy efficiency and 1.24 nW power consumption.

Designer(s): Christopher J. Lukas; Benton H. Calhoun

130nm CMOS, 2015

This 130-nm CMOS boost-converter chip enables thermoelectric energy harvesting from input voltages as low as 10 mV, supporting wearable and low-gradient thermal environments. It employs peak inductor-current control and duty-cycled, offset-compensated comparators to maintain high efficiency across wide input and output ranges, achieving 53% efficiency at 20 mV and peaking at 83% at 300 mV. The design includes robust startup mechanisms, featuring a 220 mV cold-start circuit and an RF kick-start path operating from –14.5 dBm at 915 MHz.

Designer(s): Aatmesh Shrivastava; Nathan E. Roberts; Osama U. Khan; David D. Wentzloff; Benton H. Calhoun

130nm CMOS, 2015

This 130-nm prototype implements a 512-b canary SRAM designed to track dynamic write VMIN for an accompanying 8-Kb SRAM under real operating conditions. By using reverse-assist techniques on both the bitline and wordline, the canary array produces distinct and sensitive failure signatures across voltage, temperature, and frequency variations. These characteristics allow it to reliably monitor the true write-margin limits imposed by modern process variations, enabling more accurate and adaptive VMIN control than conventional guard-banding or offline margin estimation.

Designer(s): Arijit Banerjee; Jacob Breiholz; Benton H. Calhoun

130nm CMOS, 2015

This 0.13-µm CMOS bandgap-reference chip achieves ultra-low-voltage and ultra-low-power operation with a minimum operating Vin of 500 mV and 32 nW power consumption. A 2× charge-pump-assisted bandgap core, switched-capacitor network, and low-voltage clock-generation circuitry enable reliable reference generation with 75 ppm/°C temperature stability and –40 to –52 dB PSR, without using any resistors. The design occupies only 0.0264 mm² and improves both power and minimum Vin compared with prior state-of-the-art by 1.6× and 1.4×, respectively.

Designer(s): Aatmesh Shrivastava, Kyle Craig, Nathan E. Roberts,
David D. Wentzloff, Benton H. Calhoun

130nm CMOS, 2015

This highly integrated 0.13-µm SoC serves as a flexible, self-powered platform for large-scale IoT sensing. It combines multi-source energy harvesting, including a 10-mV-startup boost converter and high-efficiency SIMO regulation, achieving up to 74.9% end-to-end efficiency. The chip incorporates a 4-channel sensing front end, sub-threshold digital system with multiple accelerators, on-chip memories operating down to 0.35 V, and an asymmetric RF subsystem that supports ultra-low-power wake-up reception and high-rate UWB transmission. With full energy autonomy and extensive processing capability, the SoC enables diverse biomedical, environmental, and motion-capture applications while maintaining system power as low as 6.45 µW during wireless streaming.

Designer(s): Alicia Klinefelter, Nathan E. Roberts, Yousef Shakhsheer, Patricia Gonzalez, Aatmesh Shrivastava, Abhishek Roy, Kyle Craig, Muhammad Faisal, James Boley, Seunghyun Oh, Yanqing Zhang, Divya Akella, David D. Wentzloff, Benton H. Calhoun

90nm CMOS, 2014

This paper presents a 32 b, 90 nm data flow processor capable of executing arbitrary DSP algorithms using fine grained Dynamic Voltage Scaling (DVS) at the component level with rapid V DD switching and V DD dithering for near-ideal quadratic dynamic energy scaling from 0.25 V-1.2 V.

Designer(s): Kyle, Yousef, Saad, Sudhanshu

130nm CMOS, 2014

This paper presents a single inductor energy harvesting and power management (EHM) unit for ultra-low power (ULP) systems. The proposed circuit harvests energy from solar cells from 0.38V input voltage (Vin) and provides 4 output voltages - storage at 5V and VDDs at 3.3V, 1.5V and 1.2V. 

Designer(s): Aatmesh

130nm CMOS, 2014

This paper presents an ultra-low power (ULP) finite-impulse response (FIR) filter using a method that approximates filter coefficients on-chip without reliance on dedicated memory such as SRAM.

Designer(s): Alicia

130nm CMOS, 2012

This chip, developed for a Body Sensor Network, is powered entirely by body-heat energy harvested through a thermoelectric generator, enabling continuous operation without a battery. It was tested on a human subject for ECG monitoring, supporting both raw-data transmission and low-power heart-rate and AFib detection modes. Depending on the mode, the chip consumes only 19–397 uW while extracting heart-rate intervals or transmitting brief ECG snippets during AFib events

Designer(s): Fan Zhang, Yanqing Zhang

130nm CMOS, 2012

This project introduces an ultra-low-power clock source for BSN chips, combining a 1 µW temperature-compensated oscillator with a 100 nW uncompensated oscillator and a fast re-locking circuit to maintain high temperature stability. Measurements from a 130 nm chip show stability comparable to a crystal oscillator while using ~7× less power and requiring no external components. This makes the design a low-cost, energy-efficient timing solution for wearable and wireless sensor networks.

Designer(s):Aatmesh