Publications

In Press

Z. Gunn, S. Hasan, A. Roy, T. Elliott, D. C. Loose, D. S. Truesdell, J. H. Lambert, and B. H. Calhoun, “Self-Powered Systems for Visibility and Trust in Supply Chains,” in 2026 IEEE Technology and Engineering Management Conference (TEMSCON), In Press.

D. C. Loose, B. H. Calhoun, D. S. Truesdell, M. C. Marcellin, M. E. Gunn, M. C. Gunn, T. L. Polmateer, I. Linkov, and J. H. Lambert, “Self-Powered Sensors Enabling Mission Level Trust in Logistics Systems and Supply Chains,” in IEEE International Symposium on Systems Engineering (ISSE), In Press.

Z. Gunn, A. Roy, S. Hasan, D. Loose, M. Gunn, D. S. Truesdell, J. H. Lambert, and B. H. Calhoun, “Self Powered Systems as Security Buttons for Improving Trust in Wildfire Sensor Nodes,” in 2026 IEEE 33rd International Conference on Electronics, Circuits and Systems, In Press.

C. D. Hess, D. S. Truesdell, and B. H. Calhoun, “Trading Complexity for Distribution: Imperceptible Fall Detection on E-Textiles,” in 2026 IEEE Biomedical Circuits and Systems Conference (BioCAS), In Press.

2026

D. S. Truesdell, J. Breiholz, and B. H. Calhoun, “Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells,” IEEE Journal of Solid-State Circuits, vol. 61, no. 10, pp. 5853–5867, Oct. 2026, doi: 10.1109/JSSC.2026.3709741. Paper Link

A. Tanaka, S. He, R. Mounesi, X. Liu, O. Faruqe, N. G. Mim, D. S. Truesdell, A. Nasiri, and B. H. Calhoun, “A Highly-Integrated Primary-Side Zero-Voltage Switching Active Clamp Flyback Control IC for a 5cm³ 5 V/1 A AC-DC Converter with Adaptive Frequency and Deadtime Control,” IEEE Journal of Solid-State Circuits, vol. 61, no. 9, pp. 5015–5026, Sep. 2026, doi: 10.1109/JSSC.2026.3693155. Paper Link

T. Elliott, A. Agrawal, D. Truesdell, and B. H. Calhoun, “Improving Wireline Fault Tolerance Using Fallback Protocols,” in 2026 IEEE 69th International Midwest Symposium on Circuits and Systems (MWSCAS), 2026, pp. 479–483, doi: 10.1109/MWSCAS67364.2026.11680748. Paper Link

J. Mack, Q. Zhang, H. Wang, Y. Shen, J. Chang, H. Yang, A. Agrawal, Z. Fan, B. Desman, Z. Lewis, T. Farrell, D. Blaauw, W. Farrell, J. Owens, B. H. Calhoun, and D. Sylvester, “TexCAC: A Direct-Textile-Attachable Microcontroller Integrating 2-MB MRAM for the Command and Control of Advanced Smart Textiles,” IEEE Journal of Solid-State Circuits, vol. 61, no. 7, pp. 3307–3316, Jul. 2026, doi: 10.1109/JSSC.2026.3695482. Paper Link

Z. Gunn, D. Truesdell, and B. H. Calhoun, “A High dv/dt-Tolerant Level Shifter with Sub-Nanosecond Delay Using Dummy Pulse Protection,” in 2026 IEEE International Symposium on Circuits and Systems (ISCAS), 2026, pp. 4395–4399, doi: 10.1109/ISCAS66217.2026.11562396. Paper Link

S. Bhattacharya, C. Hess, O. Faruqe, J. K. McElveen, D. Cairns, D. Overland, J. Johnson, D. S. Truesdell, and B. H. Calhoun, “TAuC-SoC: A 0.36 mm² In-Yarn Integrable Tiny Audio Compressor SoC for E-Textile Based Audio Recording Applications,” in 2026 IEEE International Symposium on Circuits and Systems (ISCAS), 2026, pp. 3261–3265, doi: 10.1109/ISCAS66217.2026.11561925. Paper Link

S. Hasan, Y. Wang, D. S. Truesdell, V. A. L. Sobral, J. L. Goodall, and B. H. Calhoun, “Energy-Adaptive and Delivery-Assured Batteryless LoRaWAN Image Sensing via Cross-Layer Co-Design,” in 2026 IEEE 14th International Workshop on Energy Harvesting & Energy-Neutral Sensing Systems (ENSsys), 2026, pp. 29–35, doi: 10.1109/enssys71150.2026.00011. Paper Link

Z. Chen, A. Agrawal, A. Tanaka, T. Elliott, T. Farrell, Z. Lewis, W. Farrell, J. Owens, D. S. Truesdell, and B. H. Calhoun, “THReaD: A 22.8 Mbps/node Two-dimensional Hierarchical Reconfigurable and Distributed Network for E-textiles with Fault Tolerance and Cooperative Power Management,” in 2026 IEEE Custom Integrated Circuits Conference (CICC), 2026, pp. 1–4, doi: 10.1109/cicc65509.2026.11509578. Paper Link

A. Tanaka, Z. Chen, J. Owens, W. Farrell, D. S. Truesdell, and B. H. Calhoun, “A 93% Peak Efficiency Buck Converter Enabling Operation with Variable Embroidered Yarn Inductance for Battery Powered In-textile Systems,” in 2026 IEEE Custom Integrated Circuits Conference (CICC), 2026, pp. 1–4, doi: 10.1109/cicc65509.2026.11509520. Paper Link

D. C. Loose, B. H. Calhoun, M. E. Gunn, M. C. Marcellin, D. S. Truesdell, I. Linkov, and J. H. Lambert, “Self-Powered Sensors and Risk Monitoring in Textile Supply Chains,” in 2026 3rd International Conference on Connected Innovation and Technology (ICCITX), 2026, pp. 119–124, doi: 10.1109/iccitx70146.2026.11679947. Paper Link

N. Hadifar, F. Jamshed, A. Tanaka, X. Wang, H. Shan, B. H. Calhoun, E. Santi, M. G. Allen, and A. Nasiri, “Miniaturized Primary-Side Regulated Active Clamp Flyback Converter with Custom IC and Integrated Transformer for High Power Density Applications,” in 2026 IEEE Applied Power Electronics Conference and Exposition (APEC), 2026, pp. 1975–1980, doi: 10.1109/APEC51134.2026.11516651. Paper Link

A. Agrawal, Z. Chen, B. E. Desman, J. Wang, A. Tanaka, F. Foysal, C. D. Hess, W. Farrell, J. Owens, D. S. Truesdell, and B. H. Calhoun, “kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm² SoC and bySPI Chiplets for Wearable Computing,” IEEE Journal of Solid-State Circuits, vol. 61, no. 1, pp. 103–115, Jan. 2026, doi: 10.1109/JSSC.2025.3624099. Paper Link | Chip Gallery

2025

O. Faruqe, Z. Chen, S. Bhattacharya, M. F. Foysal, S. Hasan, J. Wang, D. S. Truesdell, and B. H. Calhoun, “A Compact, Power-Efficient, and On-the-Fly I2C-to-SPI Converter for Distributed E-Textile Systems,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 12, pp. 7542–7552, Dec. 2025, doi: 10.1109/TCSI.2025.3582586. Paper Link | Chip Gallery

Q. Zhang, A. Agrawal, Z. Fan, J. Mack, B. Desman, Z. Lewis, T. Farrell, D. Blaauw, W. Farrell, J. Owens, B. H. Calhoun, and D. Sylvester, “TexCAC: A 22nm 4.8mm² 18pJ/Cycle Direct-Textile-Attachable Microcontroller Integrating 2MB MRAM for the Command and Control of Advanced Smart Textiles,” in 2025 IEEE European Solid-State Electronics Research Conference (ESSERC), 2025, pp. 405–408, doi: 10.1109/ESSERC66193.2025.11213982. Paper Link

A. Tanaka, S. He, J. Owens, W. Farrell, Z. Lewis, T. Farrell, D. S. Truesdell, and B. H. Calhoun, “A Cooperative 0.6×1.2mm Fully On-Chip Switched-Capacitor Voltage Regulator with Communication-Free Multi-Chip Output Voltage Matching for Distributed Power Management in Networks-on-Textiles,” in 2025 IEEE European Solid-State Electronics Research Conference (ESSERC), 2025, pp. 381–384, doi: 10.1109/esserc66193.2025.11213986. Paper Link | Chip Gallery

O. Faruqe, P. Le, D. Lee, X. Liu, O. Abdelatty, D. S. Truesdell, and B. H. Calhoun, “A Fully Integrated, Custom End-to-End PPG Sensing System for Ultra-Low Power Wearables,” in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 2025, pp. 1–5, doi: 10.1109/ISCAS56072.2025.11044314. Paper Link

O. Faruqe, Z. Chen, S. Bhattacharya, M. F. Foysal, S. Hasan, D. S. Truesdell, and B. H. Calhoun, “A 0.36 mm² On-the-Fly I2C-to-SPI Converter for E-Textile Applications,” in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 2025, pp. 1–5, doi: 10.1109/ISCAS56072.2025.11043981. Paper Link | Chip Gallery

N. Ownby, P. Singaraju, S. Bhattacharya, S. M. Bowers, and B. H. Calhoun, “A Sub-µW Digital Temperature Compensation Architecture for Arbitrary Voltage and Current Reference Generation,” in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 2025, pp. 1–5, doi: 10.1109/ISCAS56072.2025.11043940. Paper Link | Chip Gallery

A. Agrawal, X. Liu, D. S. Truesdell, and B. H. Calhoun, “Characterization of Stacked PV Cell Configurations in a Deep N-Well 65nm CMOS Technology,” in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 2025, pp. 1–5, doi: 10.1109/ISCAS56072.2025.11044214. Paper Link | Chip Gallery

Z. Chen, B. E. Desman, A. Agrawal, W. Farrell, J. Owens, D. S. Truesdell, and B. H. Calhoun, “ISPI: A 2-Wire Improved Serial Peripheral Interface with Automatic Routing Algorithm for 2-D In-Textile Distributed Computing and Storage Systems,” in 2025 IEEE Custom Integrated Circuits Conference (CICC), 2025, pp. 1–3, doi: 10.1109/CICC63670.2025.10982980. Paper Link | Chip Gallery

A. Tanaka, S. He, R. Mounesi, X. Liu, O. Faruqe, N. G. Mim, D. S. Truesdell, A. Nasiri, and B. H. Calhoun, “An 81.0% Peak Efficiency, 1.0W/cm³ Miniaturized 5V/1A AC-DC Converter Using a Highly-Integrated Primary-Side Active Clamp Flyback Controller with Adaptive Frequency and Zero-Voltage Switching,” in 2025 IEEE Custom Integrated Circuits Conference (CICC), 2025, pp. 1–3, doi: 10.1109/CICC63670.2025.10983408. Paper Link | Chip Gallery | Chip Gallery

A. Agrawal, Z. Chen, B. E. Desman, J. Wang, A. Tanaka, F. Foysal, C. D. Hess, W. Farrell, J. Owens, D. S. Truesdell, and B. H. Calhoun, “37.2 A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6×2.15mm² SoC and bySPI Chiplets,” in 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025, pp. 608–610, doi: 10.1109/ISSCC49661.2025.10904771. Paper Link | Chip Gallery

2024

X. Liu, A. Agrawal, A. Tanaka, and B. H. Calhoun, “Distributed Energy Harvesting and Power Management Units for Self-Powered In-Fabric Sensing Networks,” in 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS), 2024, pp. 1372–1377, doi: 10.1109/MWSCAS60917.2024.10658854. Paper Link

O. Faruqe, D. Lee, N. B. Ownby, and B. H. Calhoun, “A 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub-µW Robust Wearable Sensing,” IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 4, pp. 849–860, Aug. 2024, doi: 10.1109/TBCAS.2024.3420871. Paper Link | Chip Gallery

X. Liu, S. Kamineni, J. Breiholz, B. H. Calhoun, and S. Li, “A Sub-µW Energy-Performance-Aware IoT SoC With a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization,” IEEE Journal of Solid-State Circuits, vol. 59, no. 7, pp. 2272–2285, Jul. 2024, doi: 10.1109/JSSC.2024.3350449. Paper Link

P. Wang, R. Agarwala, N. B. Ownby, X. Liu, and B. H. Calhoun, “A 2.3–5.7 µW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2, and Pulse Transit Time Co-Monitoring,” IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 3, pp. 564–579, Jun. 2024, doi: 10.1109/TBCAS.2024.3360140. Paper Link | Chip Gallery

J. Moody, B. Magstadt, R. Costanzo, S. Yen, T. Forbes, K. Tracey, N. Ownby, P. Singaraju, S. Bhattacharya, D. Duvvuri, S. M. Bowers, and B. H. Calhoun, “A Robust Near-ZERO Power Wake-up Receiver with -108dBm Sensitivity,” in Government Microcircuit Applications and Critical Technology Conference, 2024.

X. Liu, A. Agrawal, A. Tanaka, and B. Calhoun, “8.5 A 6nA Fully-Autonomous Triple-Input Hybrid-Inductor-Capacitor Multi-Output Power Management System with Multi-Rail Energy Sharing, All-Rail Cold Startup, and Adaptive Conversion Control for mm-scale Distributed Systems,” in 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, pp. 152–154, doi: 10.1109/ISSCC49657.2024.10454435. Paper Link | Chip Gallery

S. Gupta, S. Li, and B. H. Calhoun, “Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 1, pp. 190–194, Jan. 2024, doi: 10.1109/TVLSI.2023.3328978. Paper Link

L. Zhang, D. Duvvuri, S. Bhattacharya, A. Dissanayake, X. Liu, H. L. Bishop, Y. Zhang, T. N. Blalock, B. H. Calhoun, and S. M. Bowers, “A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL,” IEEE Open Journal of the Solid-State Circuits Society, vol. 4, pp. 43–56, 2024, doi: 10.1109/OJSSCS.2024.3387388. Paper Link

2023

X. Liu, D. S. Truesdell, O. Faruqe, L. Parameswaran, M. Rickley, A. Kopanski, L. Cantley, A. Coon, M. Bernasconi, T. Wang, and B. H. Calhoun, “A 33nW Fully Autonomous SoC With Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for mm-Scale System-in-Fiber,” IEEE Transactions on Biomedical Circuits and Systems, vol. 17, no. 6, pp. 1185–1201, Dec. 2023, doi: 10.1109/TBCAS.2023.3309779. Paper Link | Chip Gallery

D. S. Truesdell, J. Boley, A. Wokhlu, A. Gravel, D. D. Wentzloff, and B. H. Calhoun, “Modeling and Design of Cold-Start Charge Pumps for Photovoltaic Energy Harvesters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 11, pp. 4334–4345, Nov. 2023, doi: 10.1109/TCSI.2023.3306308. Paper Link

X. Liu, Z. Chen, N. G. Mim, A. Agrawal, and B. H. Calhoun, “A 1pJ/bit Bypass-SPI Interconnect Bus with I²C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks,” in 2023 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2023, pp. 1–5, doi: 10.1109/BIOCAS58349.2023.10389165. Paper Link | Chip Gallery

O. Faruqe, D. Lee, N. B. Ownby, and B. H. Calhoun, “A 10-Channel, 1.2 µW, Reconfigurable Capacitance-to-Digital Converter for Low-Power, Wearable Healthcare Applications,” in 2023 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2023, doi: 10.1109/BioCAS58349.2023.10388628. Paper Link | Chip Gallery

S. Kamineni, A. Sharma, R. Harjani, S. S. Sapatnekar, and B. H. Calhoun, “AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells,” in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, pp. 1–6, doi: 10.23919/DATE56975.2023.10137270. Paper Link

L. Zhang, D. Duvvuri, S. Bhattacharya, A. Dissanayake, X. Liu, H. L. Bishop, Y. Zhang, T. N. Blalock, B. H. Calhoun, and S. M. Bowers, “A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR,” in 2023 IEEE Custom Integrated Circuits Conference (CICC), 2023, pp. 1–2, doi: 10.1109/CICC57935.2023.10121253. Paper Link | Chip Gallery

X. Liu, D. S. Truesdell, O. Faruqe, L. Parameswaran, M. Rickley, A. Kopanski, L. Cantley, A. Coon, M. Bernasconi, T. Wang, and B. H. Calhoun, “15.1 A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber,” in 2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, pp. 236–238, doi: 10.1109/ISSCC42615.2023.10067265. Paper Link | Chip Gallery

C. J. Lukas, F. B. Yahya, K.-K. Huang, J. Boley, D. S. Truesdell, J. Breiholz, A. Wokhlu, K. Craig, J. K. Brown, A. Fitting, W. Moore, A. Shih, A. Wang, A. Gravel, D. D. Wentzloff, and B. H. Calhoun, “15.2 A 2.19µW Self-Powered SoC with Integrated Multimodal Energy Harvesting, Dual-Channel up to −92dBm WRX and Energy-Aware Subsystem,” in 2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, pp. 238–240, doi: 10.1109/ISSCC42615.2023.10067337. Paper Link

2022

N. B. Ownby, K. A. Flynn, and B. H. Calhoun, “Modeling Energy Aware Photoplethysmography for Personalized Healthcare Applications,” IEEE Transactions on Biomedical Circuits and Systems, vol. 16, no. 4, pp. 570–579, Aug. 2022, doi: 10.1109/TBCAS.2022.3197128. Paper Link

X. Liu, B. H. Calhoun, and S. Li, “A Sub-nW 93% Peak Efficiency Buck Converter With Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control,” IEEE Journal of Solid-State Circuits, vol. 57, no. 7, pp. 2054–2067, Jul. 2022, doi: 10.1109/JSSC.2022.3161617. Paper Link | Chip Gallery

D. S. Truesdell, X. Liu, J. Breiholz, S. Gupta, S. Li, and B. H. Calhoun, “NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling,” in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, pp. 210–211, doi: 10.1109/VLSITechnologyandCir46769.2022.9830206. Paper Link | Chip Gallery

P. Wang and B. H. Calhoun, “A Photoplethysmography Analog Front-End Model for Rapid Design of Personalized Healthcare Hardware,” in 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, pp. 1145–1149, doi: 10.1109/ISCAS48785.2022.9937734. Paper Link

K.-K. Huang, J. K. Brown, R. K. Sawyer, C. J. Lukas, F. B. Yahya, A. Wang, N. E. Roberts, B. H. Calhoun, and D. D. Wentzloff, “ULP Receivers in Self-Powered Industrial IoT Applications: Challenges and Prospects,” in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, pp. 1–8, doi: 10.1109/CICC53496.2022.9772793. Paper Link

A. Dissanayake, H. L. Bishop, S. M. Bowers, and B. H. Calhoun, “A 2.4GHz -91.5dBm Sensitivity Within-Packet Duty-Cycled Wake-up Receiver,” IEEE Journal of Solid-State Circuits, vol. 57, no. 3, pp. 917–931, Mar. 2022, doi: 10.1109/JSSC.2021.3104540. Paper Link | Chip Gallery

X. Liu, S. Kamineni, J. Breiholz, B. H. Calhoun, and S. Li, “13.8 A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization,” in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1–3, doi: 10.1109/ISSCC42614.2022.9731758. Paper Link | Chip Gallery

S. Li, X. Liu, and B. H. Calhoun, “30.1 A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy-Harvesting and Power-Management Platform with 1.2×10⁵ Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-Up,” in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1–3, doi: 10.1109/ISSCC42614.2022.9731732. Paper Link | Chip Gallery

X. Shen, D. Duvvuri, P. Bassirian, H. L. Bishop, X. Liu, A. Dissanayake, Y. Zhang, T. N. Blalock, B. H. Calhoun, and S. M. Bowers, “A 184-nW, -78.3-dBm Sensitivity Antenna-Coupled Supply, Temperature, and Interference-Robust Wake-Up Receiver at 4.9 GHz,” IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 1, pp. 744–757, Jan. 2022, doi: 10.1109/TMTT.2021.3127550. Paper Link

P. P. Mercier, B. H. Calhoun, P.-H. P. Wang, A. Dissanayake, L. Zhang, D. A. Hall, and S. M. Bowers, “Low-Power RF Wake-Up Receivers: Analysis, Tradeoffs, and Design (Invited Paper),” IEEE Open Journal of the Solid-State Circuits Society, vol. 2, pp. 144–164, 2022, doi: 10.1109/OJSSCS.2022.3215099. Paper Link

S. Li, X. Liu, and B. H. Calhoun, “A 956pW Switched-Capacitor Sub-Bandgap Reference with 0.44-to-3.3V Supply Range, -67dB PSRR, and 0.2% within-Wafer Inaccuracy for Nanowatt IoT Systems,” accepted to ESSCIRC 2022 – IEEE 48th European Solid State Circuits Conference; TechRxiv preprint, doi: 10.36227/techrxiv.170492410.03206232/v1. Paper Link

2021

A. Mallick, M. K. Bashar, D. S. Truesdell, B. H. Calhoun, and N. Shukla, “Overcoming the Accuracy vs. Performance Trade-off in Oscillator Ising Machines,” in 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 40.2.1–40.2.4, doi: 10.1109/IEDM19574.2021.9720612. Paper Link

S. Gupta and B. H. Calhoun, “Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 12, pp. 5038–5048, Dec. 2021, doi: 10.1109/TCSI.2021.3110484. Paper Link

R. Agarwala, P. Wang, and B. H. Calhoun, “A 405nW/4.8µW Event-Driven Multi-Modal (V/I/R/C) Sensor Interface for Physiological and Environmental Co-Monitoring,” in 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021, pp. 1–4, doi: 10.1109/BIOCAS49922.2021.9644963. Paper Link

K. A. Flynn, N. B. Ownby, P. Wang, and B. H. Calhoun, “Modeling Energy-Aware Photoplethysmography Hardware for Personalized Health Care Applications Across Skin Phototypes,” in 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021, doi: 10.1109/BIOCAS49922.2021.9644946. Paper Link

X. Liu, S. Li, and B. H. Calhoun, “An 802pW 93% Peak Efficiency Buck Converter with 5.5×10⁶ Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control,” in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, pp. 347–350, doi: 10.1109/ESSCIRC53450.2021.9567744. Paper Link

X. Chen, A. Alghaihab, Y. Shi, D. S. Truesdell, B. H. Calhoun, and D. D. Wentzloff, “A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets,” IEEE Journal of Solid-State Circuits, vol. 56, no. 7, pp. 1963–1974, Jul. 2021, doi: 10.1109/JSSC.2020.3046610. Paper Link

O. Abdelatty, A. Alghaihab, Y. K. Cherivirala, S. Kamineni, B. Calhoun, and D. D. Wentzloff, “A 300µW Bluetooth-Low-Energy Backchannel Receiver Employing a Discrete-Time Differentiator-Based Coherent GFSK Demodulation,” in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021, pp. 239–242, doi: 10.1109/RFIC51843.2021.9490429. Paper Link

D. Duvvuri, X. Shen, P. Bassirian, H. L. Bishop, X. Liu, C.-H. Chen, A. Dissanayake, Y. Zhang, T. N. Blalock, B. H. Calhoun, and S. M. Bowers, “A 366 nW, −74.5 dBm Sensitivity Antenna-Coupled Wakeup Receiver at 4.9 GHz with Integrated Voltage Regulation and References,” in 2021 IEEE MTT-S International Microwave Symposium (IMS), 2021, pp. 641–645, doi: 10.1109/IMS19712.2021.9574800. Paper Link

A. Mallick, M. K. Bashar, D. S. Truesdell, B. H. Calhoun, S. Joshi, and N. Shukla, “Graph Coloring Using Coupled Oscillator-Based Dynamical Systems,” in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1–5, doi: 10.1109/ISCAS51556.2021.9401188. Paper Link

A. Dissanayake, S. M. Bowers, and B. H. Calhoun, “Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design,” in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1–4, doi: 10.1109/ISCAS51556.2021.9401499. Paper Link

S. Kamineni, S. Gupta, and B. H. Calhoun, “MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros,” in 2021 IEEE Custom Integrated Circuits Conference (CICC), 2021, pp. 1–2, doi: 10.1109/CICC51472.2021.9431501. Paper Link | Chip Gallery

R. Agarwala, P. Wang, H. L. Bishop, A. Dissanayake, and B. H. Calhoun, “A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring,” IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1058–1070, Apr. 2021, doi: 10.1109/JSSC.2021.3057229. Paper Link

D. S. Truesdell, S. Li, and B. H. Calhoun, “A 0.5-V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator With 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 56, no. 4, pp. 1241–1253, Apr. 2021, doi: 10.1109/JSSC.2020.3048664. Paper Link | Chip Gallery

S. Gupta and B. H. Calhoun, “Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 3, pp. 1171–1182, Mar. 2021, doi: 10.1109/TCSI.2020.3044836. Paper Link

K.-K. Huang, J. K. Brown, N. Collins, R. K. Sawyer, F. B. Yahya, A. Wang, N. E. Roberts, B. H. Calhoun, and D. D. Wentzloff, “21.3 A Fully Integrated 2.7µW -70.2dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End, -16.5dB-SIR, FEC and Cryptographic Checksum,” in 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 306–308, doi: 10.1109/ISSCC42613.2021.9365806. Paper Link

H. L. Bishop, A. Dissanayake, S. M. Bowers, and B. H. Calhoun, “21.5 An Integrated 2.4GHz -91.5dBm-Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2µW at 100ms Latency,” in 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 310–312, doi: 10.1109/ISSCC42613.2021.9365825. Paper Link | Chip Gallery

T. Ajayi, S. Kamineni, M. Fayazi, Y. K. Cherivirala, K. Kwon, S. Gupta, W. Duan, J. Lee, C.-H. Chen, M. Saligane, D. Sylvester, D. Blaauw, R. Dreslinski Jr, B. Calhoun, and D. D. Wentzloff, “Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation,” in IFIP Advances in Information and Communication Technology, 2021, pp. 65–85, doi: 10.1007/978-3-030-81641-4_4. Paper Link

2020

M. K. Bashar, A. Mallick, D. S. Truesdell, B. H. Calhoun, S. Joshi, and N. Shukla, “Experimental Demonstration of a Reconfigurable Coupled Oscillator Platform to Solve the Max-Cut Problem,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 2, pp. 116–121, Dec. 2020, doi: 10.1109/JXCDC.2020.3025994. Paper Link

D. S. Truesdell, S. Z. Ahmed, A. W. Ghosh, and B. H. Calhoun, “Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 2, pp. 138–145, Dec. 2020, doi: 10.1109/JXCDC.2020.3024798. Paper Link

T. Ajayi, S. Kamineni, Y. K. Cherivirala, M. Fayazi, K. Kwon, M. Saligane, S. Gupta, C.-H. Chen, D. Sylvester, D. Blaauw, R. Dreslinski, B. Calhoun, and D. D. Wentzloff, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation,” in 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020, pp. 141–146, doi: 10.1109/VLSI-SOC46417.2020.9344104. Paper Link

S. Li, J. Breiholz, S. Kamineni, J. Im, D. D. Wentzloff, and B. H. Calhoun, “An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction,” in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1–5, doi: 10.1109/ISCAS45731.2020.9180473. Paper Link | Chip Gallery

H. L. Bishop, P. Wang, and B. H. Calhoun, “Application-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systems,” in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1–5, doi: 10.1109/ISCAS45731.2020.9180900. Paper Link

A. Mallick, M. K. Bashar, D. S. Truesdell, B. H. Calhoun, S. Joshi, and N. Shukla, “Using synchronized oscillators to compute the maximum independent set,” Nature Communications, vol. 11, no. 1, Sep. 2020, doi: 10.1038/s41467-020-18445-1. Paper Link

P. Bassirian, D. Duvvuri, N. Liu, D. Truesdell, H.-Y. Tsao, N. S. Barker, B. H. Calhoun, and S. M. Bowers, “Design of an S-Band Nanowatt-Level Wakeup Receiver With Envelope Detector-First Architecture,” IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 9, pp. 3920–3929, Sep. 2020, doi: 10.1109/TMTT.2020.2987786. Paper Link

R. Agarwala, P. Wang, A. Tanneeru, B. Lee, V. Misra, and B. H. Calhoun, “An 88.6nW Ozone Pollutant Sensing Interface IC with a 159 dB Dynamic Range,” in Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, 2020, pp. 31–36, doi: 10.1145/3370748.3406579. Paper Link

J. Im, J. Breiholz, S. Li, B. Calhoun, and D. D. Wenzloff, “A Fully Integrated 0.2V 802.11ba Wake-Up Receiver with -91.5dBm Sensitivity,” in 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2020, pp. 339–342, doi: 10.1109/RFIC49505.2020.9218383. Paper Link

S. Z. Ahmed, D. S. Truesdell, Y. Tan, B. H. Calhoun, and A. W. Ghosh, “A comprehensive analysis of Auger generation impacted planar Tunnel FETs,” Solid-State Electronics, vol. 169, Art. no. 107782, Jul. 2020, doi: 10.1016/j.sse.2020.107782. Paper Link

S. Gupta, D. S. Truesdell, and B. H. Calhoun, “A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes,” in 2020 IEEE Symposium on VLSI Circuits, 2020, pp. 1–2, doi: 10.1109/VLSICircuits18222.2020.9162772. Paper Link | Chip Gallery

P. Wang, R. Agarwala, H. L. Bishop, A. Dissanayake, and B. H. Calhoun, “A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring,” in 2020 IEEE Symposium on VLSI Circuits, 2020, pp. 1–2, doi: 10.1109/VLSICircuits18222.2020.9162901. Paper Link

D. S. Truesdell, S. Li, and B. H. Calhoun, “A 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/°C Stability Using a Duty-Cycled Digital Frequency-Locked Loop,” in 2020 IEEE Symposium on VLSI Circuits, 2020, pp. 1–2, doi: 10.1109/VLSICircuits18222.2020.9162832. Paper Link | Chip Gallery

A. Dissanayake, H. L. Bishop, J. Moody, H. Muhlbauer, B. H. Calhoun, and S. M. Bowers, “A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver,” in 2020 IEEE Symposium on VLSI Circuits, 2020, pp. 1–2, doi: 10.1109/VLSICircuits18222.2020.9162785. Paper Link

S. Li and B. H. Calhoun, “Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations,” in 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, pp. 1–8, doi: 10.1109/CICC48029.2020.9075879. Paper Link

A. Dissanayake, J. Moody, H. L. Bishop, D. Truesdell, H. Muhlbauer, R. Lu, A. Gao, S. Gong, B. H. Calhoun, and S. M. Bowers, “A -108dBm Sensitivity, -28dB SIR, 130nW to 41µW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver,” in 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, doi: 10.1109/CICC48029.2020.9075907. Paper Link | Chip Gallery

P. Bassirian, D. Duvvuri, D. S. Truesdell, N. Liu, B. H. Calhoun, and S. M. Bowers, “30.1 A Temperature-Robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X-Band,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, pp. 460–462, doi: 10.1109/ISSCC19947.2020.9063015. Paper Link

J. K. Brown, D. Abdallah, J. Boley, N. Collins, K. Craig, G. Glennon, K.-K. Huang, C. J. Lukas, W. Moore, R. K. Sawyer, Y. Shakhsheer, F. B. Yahya, A. Wang, N. E. Roberts, D. D. Wentzloff, and B. H. Calhoun, “27.1 A 65nm Energy-Harvesting ULP SoC with 256kB Cortex-M0 Enabling an 89.1µW Continuous Machine Health Monitoring Wireless Self-Powered System,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, pp. 420–422, doi: 10.1109/ISSCC19947.2020.9063067. Paper Link

A. Alghaihab, X. Chen, Y. Shi, D. S. Truesdell, B. H. Calhoun, and D. D. Wentzloff, “30.7 A Crystal-Less BLE Transmitter with -86dBm Frequency-Hopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packet,” in 2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, pp. 472–474, doi: 10.1109/ISSCC19947.2020.9062935. Paper Link

D. S. Truesdell and B. H. Calhoun, “A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3–1.2-V Range or 44-fW Leakage at 0.8–2.5-V Range,” IEEE Solid-State Circuits Letters, vol. 3, pp. 502–505, 2020, doi: 10.1109/LSSC.2020.3034093. Paper Link

T. Ajayi, Y. K. Cherivirala, K. Kwon, S. Kamineni, M. Saligane, M. Fayazi, S. Gupta, C.-H. Chen, D. Sylvester, D. Blaauw, R. D. Jr., B. H. Calhoun, and D. D. Wentzloff, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform,” in Hot Chips 32 Symposium, August 16–18, 2020.

2019

S. Li, A. Roy, and B. H. Calhoun, “A Piezoelectric Energy-Harvesting System With Parallel-SSHI Rectifier and Integrated Maximum-Power-Point Tracking,” IEEE Solid-State Circuits Letters, vol. 2, no. 12, pp. 301–304, Dec. 2019, doi: 10.1109/LSSC.2019.2951394. Paper Link | Chip Gallery

J. Moody, S. Gong, B. H. Calhoun, S. M. Bowers, A. Dissanayake, H. Bishop, R. Lu, N. Liu, D. Duvvuri, A. Gao, D. Truesdell, and N. S. Barker, “A Highly Reconfigurable Bit-Level Duty-Cycled TRF Receiver Achieving −106-dBm Sensitivity and 33-nW Average Power Consumption,” IEEE Solid-State Circuits Letters, vol. 2, no. 12, pp. 309–312, Dec. 2019, doi: 10.1109/LSSC.2019.2956419. Paper Link

V. Misra, A. Bozkurt, B. H. Calhoun, S. Datta, M. Dickey, M. Kiani, J. Lach, B. Lee, J. Jur, O. Oralkan, M. Ozturk, R. Rajagopalan, S. Roundy, J. Strohmaier, S. Trolier-McKinstry, D. Vashaee, D. Wentzloff, and D. Werner, “Optimizing the energy balance to achieve autonomous self-powering for vigilant health and IoT applications,” in Journal of Physics: Conference Series, vol. 1407, no. 1, Art. no. 012001, Nov. 2019, doi: 10.1088/1742-6596/1407/1/012001. Paper Link

D. S. Truesdell and B. H. Calhoun, “Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS,” in 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019, pp. 1–2, doi: 10.1109/S3S46989.2019.9320713. Paper Link

D. S. Truesdell, A. Dissanayake, and B. H. Calhoun, “A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability,” IEEE Solid-State Circuits Letters, vol. 2, no. 10, pp. 223–226, Oct. 2019, doi: 10.1109/LSSC.2019.2946767. Paper Link | Chip Gallery

O. Abdelatty, H. Bishop, Y. Shi, X. Chen, A. Alghaihab, B. H. Calhoun, and D. D. Wentzloff, “A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator,” in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, pp. 377–380, doi: 10.1109/ESSCIRC.2019.8902902. Paper Link

D. S. Truesdell, J. Breiholz, S. Kamineni, N. Liu, A. Magyar, and B. H. Calhoun, “A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic,” IEEE Solid-State Circuits Letters, vol. 2, no. 8, pp. 57–60, Aug. 2019, doi: 10.1109/LSSC.2019.2938897. Paper Link | Chip Gallery

J. Moody, P. Bassirian, A. Roy, N. Liu, N. S. Barker, B. H. Calhoun, and S. M. Bowers, “Interference Robust Detector-First Near-Zero Power Wake-Up Receiver,” IEEE Journal of Solid-State Circuits, vol. 54, no. 8, pp. 2149–2162, Aug. 2019, doi: 10.1109/JSSC.2019.2912710. Paper Link

N. Liu, R. Agarwala, A. Dissanayake, D. S. Truesdell, S. Kamineni, and B. H. Calhoun, “A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time,” IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 1952–1959, Jul. 2019, doi: 10.1109/JSSC.2019.2911208. Paper Link | Chip Gallery

A. Alghaihab, Y. Shi, J. Breiholz, H.-S. Kim, B. H. Calhoun, and D. D. Wentzloff, “Enhanced Interference Rejection Bluetooth Low-Energy Back-Channel Receiver With LO Frequency Hopping,” IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 2019–2027, Jul. 2019, doi: 10.1109/JSSC.2019.2907160. Paper Link

S. Li, A. Roy, and B. H. Calhoun, “A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency,” in 2019 Symposium on VLSI Circuits, 2019, pp. C324–C325, doi: 10.23919/VLSIC.2019.8778144. Paper Link | Chip Gallery

J. Moody, A. Dissanayake, H. Bishop, R. Lu, N. Liu, D. Duvvuri, A. Gao, D. Truesdell, N. S. Barker, S. Gong, B. H. Calhoun, and S. M. Bowers, “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver,” in 2019 Symposium on VLSI Circuits, 2019, pp. C86–C87, doi: 10.23919/VLSIC.2019.8777956. Paper Link

C. Stephens, A. Saunders, K. Kennedy, B. Calhoun, and N. Napoli, “Detection of Multiple Levels of Hypoxia through Novel Feature Analysis and Machine Learning,” in Aerospace Medical Association, 2019.

X. Chen, J. Breiholz, F. B. Yahya, C. J. Lukas, H.-S. Kim, B. H. Calhoun, and D. D. Wentzloff, “Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4× Frequency Edge Combiner,” IEEE Journal of Solid-State Circuits, vol. 54, no. 5, pp. 1339–1350, May 2019, doi: 10.1109/JSSC.2019.2896404. Paper Link

D. S. Truesdell and B. H. Calhoun, “A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution,” in 2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, pp. 1–4, doi: 10.1109/CICC.2019.8780382. Paper Link | Chip Gallery

P. Bassirian, J. Moody, R. Lu, A. Gao, T. Manzaneque, A. Roy, N. Scott Barker, B. H. Calhoun, S. Gong, and S. M. Bowers, “Nanowatt-Level Wakeup Receiver Front Ends Using MEMS Resonators for Impedance Transformation,” IEEE Transactions on Microwave Theory and Techniques, vol. 67, no. 4, pp. 1615–1627, Apr. 2019, doi: 10.1109/TMTT.2019.2894645. Paper Link

C. J. Lukas, F. B. Yahya, J. Breiholz, A. Roy, X. Chen, H. N. Patel, N. Liu, A. Kosari, S. Li, D. Akella Kamakshi, O. Ayorinde, D. D. Wentzloff, and B. H. Calhoun, “A 1.02 µW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications,” IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 2, pp. 271–281, Apr. 2019, doi: 10.1109/TBCAS.2019.2894775. Paper Link

R. Dreslinski, D. Wentzloff, M. Fayazi, K. Kwon, D. Blaauw, D. Sylvester, B. Calhoun, M. Coltella, and D. Urquhart, “Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits,” in Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2019, 2019.

S. Gupta, K. Gupta, B. H. Calhoun, and N. Pandey, “Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 3, pp. 978–988, Mar. 2019, doi: 10.1109/TCSI.2018.2876785. Paper Link

S. Li and B. H. Calhoun, “A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×10^5 Dynamic Load Range, 99.99% Current Efficiency, and 2mV Output Voltage Ripple,” in 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, pp. 232–234, doi: 10.1109/ISSCC.2019.8662533. Paper Link | Chip Gallery

A. Banerjee and B. H. Calhoun, “A Double Pumped Single-line-cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications,” in 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), 2019, pp. 299–304, doi: 10.1109/VLSID.2019.00070. Paper Link

2018

S. Z. Ahmed, Y. Tan, D. S. Truesdell, B. H. Calhoun, and A. W. Ghosh, “Modeling tunnel field effect transistors—From interface chemistry to non-idealities to circuit level performance,” Journal of Applied Physics, vol. 124, no. 15, Oct. 2018, doi: 10.1063/1.5044434. Paper Link

D. S. Truesdell and B. H. Calhoun, “Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits,” in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018, pp. 1–2, doi: 10.1109/S3S.2018.8640174. Paper Link

N. Liu, R. Agarwala, A. Dissanayake, D. S. Truesdell, S. Kamineni, X. Chen, D. D. Wentzloff, and B. H. Calhoun, “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time,” in ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018, pp. 150–153, doi: 10.1109/ESSCIRC.2018.8494338. Paper Link | Chip Gallery

A. Kosari, J. Breiholz, N. Liu, B. H. Calhoun, and D. D. Wentzloff, “A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis,” Journal of Low Power Electronics and Applications, vol. 8, no. 3, Art. no. 27, Aug. 2018, doi: 10.3390/jlpea8030027. Paper Link

A. Banerjee, S. Kamineni, and B. H. Calhoun, “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications,” in Proceedings of the International Symposium on Low Power Electronics and Design, 2018, pp. 1–6, doi: 10.1145/3218603.3218628. Paper Link

F. B. Yahya, C. J. Lukas, and B. H. Calhoun, “A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things,” Journal of Low Power Electronics and Applications, vol. 8, no. 2, Art. no. 21, Jun. 2018, doi: 10.3390/jlpea8020021. Paper Link

X. Chen, J. Breiholz, F. Yahya, C. Lukas, H.-S. Kim, B. Calhoun, and D. Wentzloff, “A 486 µW All-Digital Bluetooth Low Energy Transmitter with Ring Oscillator Based ADPLL for IoT applications,” in 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018, pp. 168–171, doi: 10.1109/RFIC.2018.8428960. Paper Link

A. Alghaihab, J. Breiholz, H.-S. Kim, B. Calhoun, and D. D. Wentzloff, “A 150 µW −57.5 dBm-Sensitivity Bluetooth Low-Energy Back-Channel Receiver with LO Frequency Hopping,” in 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018, pp. 324–327, doi: 10.1109/RFIC.2018.8428958. Paper Link

H. L. Bishop, P. Wang, D. Fan, J. Lach, and B. H. Calhoun, “Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy Harvesting Embedded Systems,” in 2018 Global Internet of Things Summit (GIoTS), 2018, pp. 1–6, doi: 10.1109/GIOTS.2018.8534559. Paper Link

C. J. Lukas, F. B. Yahya, and B. H. Calhoun, “An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches,” in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, pp. 1–4, doi: 10.1109/ISCAS.2018.8350959. Paper Link

D. A. Kamakshi, X. Guo, H. N. Patel, M. R. Stan, and B. H. Calhoun, “A Post-Silicon Hold Time Closure Technique using Data-Path Tunable-Buffers for Variation-Tolerance in Sub-threshold Designs,” in 2018 19th International Symposium on Quality Electronic Design (ISQED), 2018, pp. 341–346, doi: 10.1109/ISQED.2018.8357310. Paper Link

O. A. Ayorinde, H. Qi, and B. H. Calhoun, “FGC: A Toolflow for Generating and Configuring Custom FPGAs,” in Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018, pp. 294–294, doi: 10.1145/3174243.3174997. Paper Link

J. Moody, P. Bassirian, A. Roy, N. Liu, S. Pancrazio, N. S. Barker, B. H. Calhoun, and S. M. Bowers, “A −76dBm 7.4nW Wakeup Radio with Automatic Offset Compensation,” in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 452–454, doi: 10.1109/ISSCC.2018.8310379. Paper Link

S. M. Bowers, P. Bassirian, A. Gao, T. Manzaneque, A. Roy, J. Moody, B. H. Calhoun, and S. Gong, “Nanowatt Level Wake-up Receivers Using Co-Designed CMOS-MEMS Technologies,” in Government Microcircuit Applications and Critical Technology Conference, 2018.

2017

H. N. Patel, D. S. Truesdell, J. Breiholz, and B. H. Calhoun, “Ultra-Low Power Hardware Platform Enablement for IoT Sensor Systems,” in IBM CAS event, 2017.

A. Banerjee, H. N. Patel, and B. H. Calhoun, “Ultra-Low Power SRAM Design for Portable BSN and Cognitive IoT Systems,” in IBM CAS event, 2017.

H. Qi, O. Ayorinde, and B. H. Calhoun, “An Ultra-Low-Power FPGA for IoT Applications,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, pp. 1–3, doi: 10.1109/S3S.2017.8308753. Paper Link | Chip Gallery

D. A. Kamakshi, H. N. Patel, A. Roy, and B. H. Calhoun, “A 28 nW CMOS Supply Voltage Monitor for Adaptive Ultra-Low Power IoT Chips,” in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017, pp. 1–2, doi: 10.1109/S3S.2017.8344104. Paper Link

C. J. Lukas, F. B. Yahya, and B. H. Calhoun, “Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-low Power Systems,” in 2017 IEEE International Test Conference (ITC), 2017, pp. 1–10, doi: 10.1109/TEST.2017.8242039. Paper Link

P. Bassirian, J. Moody, A. Gao, T. Manzaneque, B. H. Calhoun, N. S. Barker, S. Gong, and S. M. Bowers, “A Passive 461 MHz AlN-CMOS RF Front-end for Event-driven Wakeup Receivers,” in 2017 IEEE SENSORS, 2017, pp. 1–3, doi: 10.1109/icsens.2017.8234415. Paper Link

J. Moody, P. Bassirian, A. Roy, Y. Feng, S. Li, R. Costanzo, N. S. Barker, B. Calhoun, and S. M. Bowers, “An 8.3 nW −72 dBm Event Driven IoE Wake Up Receiver RF Front End,” in 2017 12th European Microwave Integrated Circuits Conference (EuMIC), 2017, pp. 77–80, doi: 10.23919/eumic.2017.8230664. Paper Link

F. B. Yahya, C. J. Lukas, B. H. Calhoun, and S. Bartling, “FAR: A 4.12µW Ferro-electric Auto-Recovery for Battery-less BSN SoCs,” in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2017, pp. 1–4, doi: 10.1109/BIOCAS.2017.8325082. Paper Link

C. J. Lukas, B. H. Calhoun, R. Bhakta, and J. S. Jur, “A 3.77 nW, 11.4 fJ/b/mm Link for Reliable Wireline Communication in Ultra-Low Power On-Body Sensor Networks,” in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2017, pp. 1–4, doi: 10.1109/BIOCAS.2017.8325124. Paper Link | Chip Gallery

A. Roy and B. H. Calhoun, “A 71% Efficient Energy Harvesting and Power Management Unit for sub-μW Power Biomedical Applications,” in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2017, doi: 10.1109/biocas.2017.8325069. Paper Link | Chip Gallery

N. Shafiee, S. Tewari, B. Calhoun, and A. Shrivastava, “Infrastructure Circuits for Lifetime Improvement of Ultra-Low Power IoT Devices,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 9, pp. 2598–2610, Sep. 2017, doi: 10.1109/TCSI.2017.2693181. Paper Link

C. T. Murphy, C. Reichmuth, W. C. Eberhardt, B. H. Calhoun, and D. A. Mann, “Seal Whiskers Vibrate Over Broad Frequencies During Hydrodynamic Tracking,” Scientific Reports, vol. 7, no. 1, Aug. 2017, doi: 10.1038/s41598-017-07676-w. Paper Link

J. Breiholz, F. Yahya, C. J. Lukas, X. Chen, K. Leach, D. Wentzloff, and B. H. Calhoun, “A 4.4 nW Lossless Sensor Data Compression Accelerator for 2.9x System Power Reduction in Wireless Body Sensors,” in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 1041–1044, doi: 10.1109/MWSCAS.2017.8053105. Paper Link | Chip Gallery

H. N. Patel, F. B. Yahya, and B. H. Calhoun, “Subthreshold SRAM: Challenges, Design Decisions, and Solutions,” in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, pp. 321–324, doi: 10.1109/MWSCAS.2017.8052925. Paper Link

H. N. Patel, B. H. Calhoun, and R. W. Mann, “Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications,” in 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, pp. 209–210, doi: 10.1109/IOLTS.2017.8046222. Paper Link

F. Yahya, C. J. Lukas, J. Breiholz, A. Roy, H. N. Patel, N. Liu, X. Chen, A. Kosari, S. Li, D. Akella, O. Ayorinde, D. Wentzloff, and B. H. Calhoun, “A Battery-less 507nW SoC with Integrated Platform Power Manager and SiP Interfaces,” in 2017 Symposium on VLSI Circuits, 2017, doi: 10.23919/VLSIC.2017.8008532. Paper Link

A. Banerjee, N. Liu, H. N. Patel, B. H. Calhoun, J. Poulton, and C. T. Gray, “A 256kb 6T Self-Tuning SRAM with Extended 0.38V-1.2V Operating Range using Multiple Read/Write Assists and VMIN Tracking Canary Sensors,” in 2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, pp. 1–4, doi: 10.1109/cicc.2017.7993688. Paper Link | Chip Gallery | Chip Gallery

S. Ahmed, Y. Tan, D. Truesdell, and A. Ghosh, “Auger effect limited performance in tunnel field effect transistors,” in 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), Berkeley, CA, 19–20 Oct 2017, doi: 10.1109/E3S.2017.8246156. Paper Link

2016

P. Long, J. Z. Huang, M. Povolotskyi, D. Verreck, J. Charles, T. Kubis, G. Klimeck, M. J. W. Rodwell, and B. H. Calhoun, “A Tunnel FET Design for High-Current, 120 mV Operation,” in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 30.2.1–30.2.4, doi: 10.1109/IEDM.2016.7838511. Paper Link

H. Qi, O. Ayorinde, and B. H. Calhoun, “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating,” in 2016 International Conference on Field-Programmable Technology (FPT), 2016, pp. 20–27, doi: 10.1109/FPT.2016.7929183. Paper Link

H. N. Patel, A. Roy, F. B. Yahya, N. Liu, B. Calhoun, K. Kumeno, M. Yasuda, A. Harada, and T. Ema, “A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic,” in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 45–48, doi: 10.1109/ESSCIRC.2016.7598239. Paper Link | Chip Gallery

W. C. Eberhardt, B. F. Wakefield, C. T. Murphy, C. Casey, Y. Shakhsheer, B. H. Calhoun, and C. Reichmuth, “Development of an artificial sensor for hydrodynamic detection inspired by a seal's whisker array,” Bioinspiration & Biomimetics, vol. 11, no. 5, Art. no. 056011, Aug. 2016, doi: 10.1088/1748-3190/11/5/056011. Paper Link

N. Liu and B. Calhoun, “Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool,” in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, pp. 535–540, doi: 10.1109/ISVLSI.2016.50. Paper Link

Y. Huang, A. Shrivastava, L. Barnes, and B. Calhoun, “A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs,” Journal of Low Power Electronics and Applications, vol. 6, no. 3, Art. no. 11, Jun. 2016, doi: 10.3390/jlpea6030011. Paper Link | Chip Gallery

D. Akella Kamakshi, A. Shrivastava, and B. Calhoun, “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications,” Journal of Low Power Electronics and Applications, vol. 6, no. 2, Art. no. 10, Jun. 2016, doi: 10.3390/jlpea6020010. Paper Link

F. Yahya, H. Patel, J. Boley, A. Banerjee, and B. Calhoun, “A Sub-Threshold 8T SRAM Macro with 12.29 nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs,” Journal of Low Power Electronics and Applications, vol. 6, no. 2, Art. no. 8, May 2016, doi: 10.3390/jlpea6020008. Paper Link | Chip Gallery

D. Kamakshi, A. Shrivastava, C. Duan, and B. Calhoun, “A 36 nW, 7 ppm/°C On-Chip Clock Source Platform for Near-Human-Body Temperature Applications,” Journal of Low Power Electronics and Applications, vol. 6, no. 2, Art. no. 7, May 2016, doi: 10.3390/jlpea6020007. Paper Link | Chip Gallery

A. Roy and B. H. Calhoun, “Exploring Circuit Robustness to Power Supply Variation in Low-Voltage Latch and Register-Based Digital Systems,” in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 273–276, doi: 10.1109/ISCAS.2016.7527223. Paper Link | Chip Gallery

D. A. Kamakshi, M. Fojtik, B. Khailany, S. Kudva, Y. Zhou, and B. H. Calhoun, “Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks,” in 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2016, pp. 75–82, doi: 10.1109/ASYNC.2016.13. Paper Link

H. N. Patel, F. B. Yahya, and B. H. Calhoun, “Optimizing SRAM Bitcell Reliability and Energy for IoT Applications,” in 2016 17th International Symposium on Quality Electronic Design (ISQED), 2016, pp. 12–17, doi: 10.1109/ISQED.2016.7479149. Paper Link

A. Roy, P. J. Grossmann, S. A. Vitale, and B. H. Calhoun, “A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications,” in 2016 17th International Symposium on Quality Electronic Design (ISQED), 2016, pp. 158–162, doi: 10.1109/ISQED.2016.7479193. Paper Link | Chip Gallery

A. Shrivastava, D. Akella Kamakshi, and B. H. Calhoun, “A 1.5 nW, 32.768 kHz XTAL Oscillator Operational From a 0.3 V Supply,” IEEE Journal of Solid-State Circuits, vol. 51, no. 3, pp. 686–696, Mar. 2016, doi: 10.1109/JSSC.2015.2512382. Paper Link | Chip Gallery

H. N. Patel, F. B. Yahya, and B. H. Calhoun, “Improving Reliability and Energy Requirements of Memory in Body Sensor Networks,” in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016, pp. 561–562, doi: 10.1109/VLSID.2016.37. Paper Link

N. E. Roberts, K. Craig, A. Shrivastava, S. N. Wooters, Y. Shakhsheer, B. H. Calhoun, and D. D. Wentzloff, “26.8 A 236nW −56.5dBm-Sensitivity Bluetooth Low-Energy Wakeup Receiver with Energy Harvesting in 65nm CMOS,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, pp. 450–451, doi: 10.1109/isscc.2016.7418101. Paper Link

2015

A. Roy, A. Klinefelter, F. B. Yahya, X. Chen, L. P. Gonzalez-Guerrero, C. J. Lukas, D. A. Kamakshi, J. Boley, K. Craig, M. Faisal, S. Oh, N. E. Roberts, Y. Shakhsheer, A. Shrivastava, D. P. Vasudevan, D. D. Wentzloff, and B. H. Calhoun, “A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems,” IEEE Transactions on Biomedical Circuits and Systems, vol. 9, no. 6, pp. 862–874, Dec. 2015, doi: 10.1109/TBCAS.2015.2498643. Paper Link

J. Boley, P. Beshay, and B. Calhoun, “Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 12, pp. 3109–3113, Dec. 2015, doi: 10.1109/TVLSI.2014.2385832. Paper Link

Y. Huang, A. Shrivastava, and B. H. Calhoun, “A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs,” in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, pp. 1–3, doi: 10.1109/S3S.2015.7333489. Paper Link

D. A. Kamakshi, A. Shrivastava, and B. H. Calhoun, “A 23 nW CMOS Ultra-Low Power Temperature Sensor Operational from 0.2 V,” in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015, pp. 1–3, doi: 10.1109/S3S.2015.7333498. Paper Link

O. Ayorinde, H. Qi, Y. Huang, and B. H. Calhoun, “Using Island-Style Bi-Directional Intra-CLB Routing in Low-Power FPGAs,” in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, pp. 1–7, doi: 10.1109/FPL.2015.7293945. Paper Link

H. Qi, O. Ayorinde, Y. Huang, and B. Calhoun, “Optimizing Energy Efficient Low-Swing Interconnect for Sub-threshold FPGAs,” in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, pp. 1–4, doi: 10.1109/FPL.2015.7293979. Paper Link

A. Banerjee, J. Breiholz, and B. H. Calhoun, “A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations,” in 2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, pp. 1–4, doi: 10.1109/CICC.2015.7338495. Paper Link | Chip Gallery

B. Calhoun and D. Wentzloff, “Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT,” in 2015 IEEE Hot Chips 27 Symposium (HCS), 2015, pp. 1–45, doi: 10.1109/HOTCHIPS.2015.7477327. Paper Link

F. B. Yahya, H. N. Patel, V. Chandra, and B. H. Calhoun, “Combined SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation,” in 2015 6th Asia Symposium on Quality Electronic Design (ASQED), 2015, pp. 1–6, doi: 10.1109/ACQED.2015.7273998. Paper Link

A. Shrivastava, N. E. Roberts, O. U. Khan, D. D. Wentzloff, and B. H. Calhoun, “A 10 mV-Input Boost Converter With Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting With 220 mV Cold-Start and −14.5 dBm, 915 MHz RF Kick-Start,” IEEE Journal of Solid-State Circuits, vol. 50, no. 8, pp. 1820–1832, Aug. 2015, doi: 10.1109/JSSC.2015.2412952. Paper Link | Chip Gallery

C. J. Lukas and B. H. Calhoun, “A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems,” in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 2860–2863, doi: 10.1109/ISCAS.2015.7169283. Paper Link | Chip Gallery

A. Klinefelter, J. Ryan, J. Tschanz, and B. H. Calhoun, “Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications,” in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 2361–2364, doi: 10.1109/ISCAS.2015.7169158. Paper Link | Chip Gallery

V. Misra, A. Bozkurt, B. Calhoun, T. Jackson, J. Jur, J. Lach, B. Lee, J. Muth, O. Oralkan, M. Ozturk, S. Trolier-McKinstry, D. Vashaee, D. Wentzloff, and Y. Zhu, “Flexible Technologies for Self-Powered Wearable Health and Environmental Sensing,” Proceedings of the IEEE, vol. 103, no. 4, pp. 665–681, Apr. 2015, doi: 10.1109/JPROC.2015.2412493. Paper Link

J. Boley and B. Calhoun, “Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset,” in Sixteenth International Symposium on Quality Electronic Design, 2015, pp. 1–4, doi: 10.1109/ISQED.2015.7085369. Paper Link

A. Shrivastava, K. Craig, N. E. Roberts, D. D. Wentzloff, and B. H. Calhoun, “5.4 A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-low Power Systems,” in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015, pp. 1–3, doi: 10.1109/ISSCC.2015.7062942. Paper Link | Chip Gallery

A. Klinefelter, N. E. Roberts, Y. Shakhsheer, P. Gonzalez, A. Shrivastava, A. Roy, K. Craig, M. Faisal, J. Boley, S. Oh, Y. Zhang, D. Akella, D. D. Wentzloff, and B. H. Calhoun, “21.3 A 6.45µW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios,” in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015, pp. 1–3, doi: 10.1109/ISSCC.2015.7063087. Paper Link | Chip Gallery

Y. Shakhsheer, A. Shrivastava, N. Roberts, K. Craig, S. Wooters, D. D. Wentzloff, and B. H. Calhoun, “Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors,” in Government Microcircuit Applications and Critical Technology Conference (GOMACTech 2015), session "Ultra Low Power Electronics", 2015.

2014

A. Klinefelter and B. H. Calhoun, “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs,” in 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014, pp. 1–2, doi: 10.1109/S3S.2014.7028193. Paper Link | Chip Gallery

J. Bolus, B. Calhoun, and T. Blalock, “39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation,” Journal of Low Power Electronics and Applications, vol. 4, no. 3, pp. 252–267, Sep. 2014, doi: 10.3390/jlpea4030252. Paper Link

A. Shrivastava, D. Wentzloff, and B. H. Calhoun, “A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting,” in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, pp. 1–4, doi: 10.1109/CICC.2014.6946057. Paper Link

P. Beshay, V. Chandra, R. Aitken, and B. H. Calhoun, “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM,” in Proceedings of the 2014 international symposium on Low power electronics and design, 2014, pp. 307–310, doi: 10.1145/2627369.2627662. Paper Link

A. Shrivastava, Y. K. Ramadass, S. Khanna, S. Bartling, and B. H. Calhoun, “A 1.2µW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83–92% Efficiency Across Wide Input and Output Voltages,” in 2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014, pp. 1–2, doi: 10.1109/VLSIC.2014.6858364. Paper Link | Chip Gallery

A. Banerjee and B. Calhoun, “An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications,” Journal of Low Power Electronics and Applications, vol. 4, no. 2, pp. 119–137, May 2014, doi: 10.3390/jlpea4020119. Paper Link

J. Boley, B. Calhoun, V. Chandra, and R. Aitken, “Modeling SRAM Dynamic VMIN,” in 2014 IEEE International Conference on IC Design & Technology, 2014, pp. 1–4, doi: 10.1109/ICICDT.2014.6838609. Paper Link

S. Arrabi, D. Moore, L. Wang, K. Skadron, B. H. Calhoun, J. Lach, and B. H. Meyer, “Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems,” in 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines, 2014, pp. 236–236, doi: 10.1109/FCCM.2014.71. Paper Link

Y. Zhang and B. H. Calhoun, “Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits,” in Fifteenth International Symposium on Quality Electronic Design, 2014, pp. 243–248, doi: 10.1109/isqed.2014.6783332. Paper Link

A. Banerjee, M. E. Sinangil, J. Poulton, C. T. Gray, and B. H. Calhoun, “A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs,” in Fifteenth International Symposium on Quality Electronic Design, 2014, pp. 1–8, doi: 10.1109/isqed.2014.6783299. Paper Link

K. Craig, Y. Shakhsheer, S. Arrabi, S. Khanna, J. Lach, and B. H. Calhoun, “A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance,” IEEE Journal of Solid-State Circuits, vol. 49, no. 2, pp. 545–552, Feb. 2014, doi: 10.1109/jssc.2013.2285384. Paper Link | Chip Gallery

S. Khanna, S. V. Nalam, and B. H. Calhoun, “Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories,” in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, pp. 139–144, doi: 10.1109/vlsid.2014.31. Paper Link

J. J. Granacki, B. H. Calhoun, A. R. Dasu, M. Jagasivamani, L. McIlrath, and M. Fritze, “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications,” in Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2014, 2014.

2013

Y. Zhang and B. H. Calhoun, “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method,” in 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, pp. 1–2, doi: 10.1109/s3s.2013.6716531. Paper Link

A. Banerjee and B. H. Calhoun, “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM Bitcell,” in 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, pp. 1–2, doi: 10.1109/S3S.2013.6716577. Paper Link

C. T. Murphy, W. C. Eberhardt, B. H. Calhoun, K. A. Mann, and D. A. Mann, “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae,” PLoS ONE, vol. 8, no. 7, Art. no. e69872, Jul. 2013, doi: 10.1371/journal.pone.0069872. Paper Link

A. Shrivastava and B. Calhoun, “A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications,” Journal of Low Power Electronics and Applications, vol. 3, no. 3, pp. 215–232, Jun. 2013, doi: 10.3390/jlpea3030215. Paper Link

P. Beshay, J. Ryan, and B. Calhoun, “A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers,” Journal of Low Power Electronics and Applications, vol. 3, no. 2, pp. 159–173, May 2013, doi: 10.3390/jlpea3020159. Paper Link

A. Shrivastava, J. Pandey, B. Otis, and B. H. Calhoun, “A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node,” in 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013, pp. 72–75, doi: 10.1109/VLSID.2013.165. Paper Link

Y. Zhang, F. Zhang, Y. Shakhsheer, J. D. Silver, A. Klinefelter, M. Nagaraju, J. Boley, J. Pandey, A. Shrivastava, E. J. Carlson, A. Wood, B. H. Calhoun, and B. P. Otis, “A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications,” IEEE Journal of Solid-State Circuits, vol. 48, no. 1, pp. 199–213, Jan. 2013, doi: 10.1109/JSSC.2012.2221217. Paper Link

J. Boley, P. Beshay, and B. H. Calhoun, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization,” in SRC TECHCON 2013, 2013.

N. Gilbert, Y. Zhang, J. Dinh, B. H. Calhoun, and S. Hollmer, “A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications,” in 2013 Symposium on VLSI Circuits, 2013.

J. Boley, V. Chandra, R. Aitken, and B. Calhoun, “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic Write VMIN,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, pp. 1819–1824, doi: 10.7873/DATE.2013.364. Paper Link

2012

A. M. Klinefelter, Y. Zhang, B. Otis, and B. H. Calhoun, “A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 12, pp. 937–941, Dec. 2012, doi: 10.1109/TCSII.2012.2231041. Paper Link

S. N. Wooters, A. C. Cabe, Z. Qi, J. Wang, R. W. Mann, B. H. Calhoun, M. R. Stan, and T. N. Blalock, “Tracking On-Chip Age Using Distributed, Embedded Sensors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 11, pp. 1974–1985, Nov. 2012, doi: 10.1109/TVLSI.2011.2168246. Paper Link

P. Beshay, J. Bolus, T. Blalock, V. Chandra, and B. H. Calhoun, “SRAM Sense Amplifier Offset Cancellation Using BTI Stress,” in 2012 IEEE Subthreshold Microelectronics Conference (SubVT), 2012, pp. 1–3, doi: 10.1109/SubVT.2012.6404299. Paper Link

P. Beshay, B. H. Calhoun, and J. F. Ryan, “Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry,” in 2012 IEEE Subthreshold Microelectronics Conference (SubVT), 2012, pp. 1–3, doi: 10.1109/SubVT.2012.6404300. Paper Link

A. Shrivastava and B. H. Calhoun, “Modeling DC-DC Converter Efficiency and Power Management in Ultra Low Power Systems,” in 2012 IEEE Subthreshold Microelectronics Conference (SubVT), 2012, doi: 10.1109/SubVT.2012.6404315. Paper Link

L. Szafaryn, J. Chen, B. H. Calhoun, J. Lach, K. Skadron, and B. H. Meyer, “Reducing the Cost of Safety-critical Systems with On-demand Redundancy,” in SRC TECHCON 2012, 2012.

Y. Shakhsheer, Y. Zhang, B. Otis, and B. H. Calhoun, “A Custom Processor for Node and Power Management of a Battery-less Body Sensor Node in 130nm CMOS,” in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, pp. 1–4, doi: 10.1109/CICC.2012.6330705. Paper Link

A. Shrivastava and B. H. Calhoun, “A 150nW, 5ppm/°C, 100kHz On-Chip Clock Source for Ultra Low Power SoCs,” in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, pp. 1–4, doi: 10.1109/CICC.2012.6330699. Paper Link | Chip Gallery

K. Craig, Y. Shakhsheer, and B. H. Calhoun, “Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation,” in Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2012, pp. 221–224, doi: 10.1145/2333660.2333714. Paper Link

K. Craig, Y. Shakhsheer, S. Khanna, S. Arrabi, J. Lach, B. H. Calhoun, and S. Kosonocky, “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs,” in Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2012, pp. 167–172, doi: 10.1145/2333660.2333703. Paper Link

A. Shrivastava, J. Lach, and B. Calhoun, “A Charge Pump Based Receiver Circuit for Voltage Scaled Interconnect,” in Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2012, pp. 327–332, doi: 10.1145/2333660.2333733. Paper Link

R. W. Mann, T. B. Hook, P. T. Nguyen, and B. H. Calhoun, “Nonrandom Device Mismatch Considerations in Nanoscale SRAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 7, pp. 1211–1220, Jul. 2012, doi: 10.1109/tvlsi.2011.2158863. Paper Link

J. Boley, J. Wang, and B. H. Calhoun, “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN,” Journal of Low Power Electronics and Applications, vol. 2, no. 2, pp. 143–154, Apr. 2012, doi: 10.3390/jlpea2020143. Paper Link

F. Zhang, Y. Zhang, J. Silver, Y. Shakhsheer, M. Nagaraju, A. Klinefelter, J. Pandey, J. Boley, E. Carlson, A. Shrivastava, B. Otis, and B. Calhoun, “A Batteryless 19µW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC,” in 2012 IEEE International Solid-State Circuits Conference, 2012, pp. 298–300, doi: 10.1109/ISSCC.2012.6177004. Paper Link | Chip Gallery

B. H. Calhoun, J. Lach, J. Stankovic, D. D. Wentzloff, K. Whitehouse, A. T. Barth, J. K. Brown, Q. Li, S. Oh, N. E. Roberts, and Y. Zhang, “Body Sensor Networks: A Holistic Approach from Silicon to Users,” Proceedings of the IEEE, vol. 100, no. 1, pp. 91–106, Jan. 2012, doi: 10.1109/JPROC.2011.2161240. Paper Link

B. H. Calhoun, S. E. R. T. Howe, and C. G. Sodini, “Design Principles for Digital CMOS Integrated Circuits,” in National Technology & Science Press (NTS Press), The Modular Series of Microelectronic Device & Circuit Design, 2012.

L. Wang, K. Skadron, and B. Calhoun, “Dark vs. Dim Silicon and Near-Threshold Computing,” in Dark Silicon Workshop (DaSi) 2012, 2012.

2011

J. Wang and B. H. Calhoun, “Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 11, pp. 2120–2125, Nov. 2011, doi: 10.1109/TVLSI.2010.2071890. Paper Link

B. H. Meyer, B. H. Calhoun, J. Lach, and K. Skadron, “Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy,” in Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems, 2011, pp. 125–134, doi: 10.1145/2038698.2038719. Paper Link

W. C. Eberhardt, Y. A. Shakhsheer, B. H. Calhoun, J. R. Paulus, and M. Appleby, “A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability,” in 2011 IEEE SENSORS Proceedings, 2011, pp. 982–985, doi: 10.1109/ICSENS.2011.6127266. Paper Link

S. Nalam and B. H. Calhoun, “5T SRAM with Asymmetric Sizing for Improved Read Stability,” IEEE Journal of Solid-State Circuits, vol. 46, no. 10, pp. 2431–2442, Oct. 2011, doi: 10.1109/JSSC.2011.2160812. Paper Link | Chip Gallery

Y. Shakhsheer, S. Khanna, K. Craig, S. Arrabi, J. Lach, and B. H. Calhoun, “A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V,” in 2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, pp. 1–4, doi: 10.1109/CICC.2011.6055335. Paper Link | Chip Gallery

J. F. Ryan, S. Khanna, and B. H. Calhoun, “An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal,” in IEEE/ACM International Symposium on Low Power Electronics and Design, 2011, pp. 297–302, doi: 10.1109/ISLPED.2011.5993653. Paper Link

J. Wang, A. Hoefler, and B. H. Calhoun, “An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 5, pp. 909–914, May 2011, doi: 10.1109/TVLSI.2010.2042184. Paper Link | Chip Gallery

Y. Zhang, Y. Shakhsheer, A. T. Barth, H. C. Powell Jr., S. A. Ridenour, M. A. Hanson, J. Lach, and B. H. Calhoun, “Energy Efficient Design for Body Sensor Nodes,” Journal of Low Power Electronics and Applications, vol. 1, no. 1, pp. 109–130, Apr. 2011, doi: 10.3390/jlpea1010109. Paper Link

S. Khanna, K. Craig, Y. Shakhsheer, S. Arrabi, J. Lach, and B. H. Calhoun, “Stepped Supply Voltage Switching for Energy Constrained Systems,” in 2011 12th International Symposium on Quality Electronic Design, 2011, pp. 1–6, doi: 10.1109/ISQED.2011.5770803. Paper Link

R. W. Mann and B. H. Calhoun, “New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm,” in 2011 12th International Symposium on Quality Electronic Design, 2011, pp. 1–6, doi: 10.1109/isqed.2011.5770761. Paper Link

S. Nalam, V. Chandra, R. C. Aitken, and B. H. Calhoun, “Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs,” in 2011 Design, Automation & Test in Europe, 2011, pp. 1–6, doi: 10.1109/date.2011.5763081. Paper Link

B. H. Meyer, N. George, B. Calhoun, J. Lach, and K. Skadron, “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication,” in 2011 Design, Automation & Test in Europe, 2011, pp. 1–6, doi: 10.1109/DATE.2011.5763200. Paper Link

Y. Zhang and B. H. Calhoun, “The Cost of Fixing Hold Time Violations in Sub-threshold Circuits,” in IEEE Subthreshold Microelectronics Conference, 2011.

K. Craig, Y. Shakhsheer, S. Khanna, and B. H. Calhoun, “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling enabling Sub-threshold Operation,” in IEEE Subthreshold Microelectronics Conference (SubVT) 2011, 2011.

J. Boley and B. H. Calhoun, “Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin,” in IEEE Subthreshold Microelectronics Conference (SubVT) 2011, 2011.

A. Shrivastava and B. H. Calhoun, “A sub-threshold clock and data recovery circuit for a wireless sensor node receiver,” in IEEE Subthreshold Microelectronics Conference (SubVT 2011), 2011.

A. Klinefelter and B. H. Calhoun, “A Programmable Multi-channel Sub-threshold FIR Filter for a Body Area Sensor Node,” in IEEE Subthreshold Microelectronics Conference (SubVT 2011), 2011.

B. H. Calhoun and J. Lach, “What is a Body Sensor Network?,” in ACM/SIGDA E-Newsletter, 2011.

Y. Yao, J. Huang, S. Khanna, A. shelat, B. H. Calhoun, J. Lach, and D. Evans, “A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm CMOS,” in Cryptology and Information Security Series, 2011, doi: 10.3233/978-1-60750-722-2-96. Paper Link

C. T. Murphy, W. C. Eberhardt, B. H. Calhoun, and D. A. Mann, “Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception,” in Biennial Conference on the Biology of Marine Mammals, 2011.

B. H. Calhoun, Y. Zhang, S. Khanna, K. Craig, Y. Shakhsheer, and J. Lach, “A Sub-threshold FPGA: Energy Efficient Reconfigurable Logic,” in Government Microcircuit Applications and Critical Technology Conference, 2011.

2010

J. Wang, A. Singhee, R. A. Rutenbar, and B. H. Calhoun, “Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1908–1920, Dec. 2010, doi: 10.1109/TCAD.2010.2061810. Paper Link

R. W. Mann, J. Wang, S. Nalam, S. Khanna, G. Braceras, H. Pilo, and B. H. Calhoun, “Impact of circuit assist methods on margin and performance in 6T SRAM,” Solid-State Electronics, vol. 54, no. 11, pp. 1398–1407, Nov. 2010, doi: 10.1016/j.sse.2010.06.009. Paper Link

J. B. Stocking, W. C. Eberhardt, Y. A. Shakhsheer, B. H. Calhoun, J. R. Paulus, and M. Appleby, “A Capacitance-based Whisker-like Artificial Sensor for Fluid Motion Sensing,” in 2010 IEEE Sensors, 2010, pp. 2224–2229, doi: 10.1109/ICSENS.2010.5690637. Paper Link

J. Wang, S. Nalam, Z. Qi, R. W. Mann, M. Stan, and B. H. Calhoun, “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress,” in IEEE Custom Integrated Circuits Conference 2010, 2010, pp. 1–4, doi: 10.1109/CICC.2010.5617631. Paper Link

J. F. Ryan and B. H. Calhoun, “A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS,” in IEEE Custom Integrated Circuits Conference 2010, 2010, pp. 1–4, doi: 10.1109/cicc.2010.5617466. Paper Link

B. H. Calhoun and D. Brooks, “Can Subthreshold and Near-Threshold Circuits Go Mainstream?,” in IEEE Micro, vol. 30, no. 4, pp. 80–85, Jul. 2010, doi: 10.1109/MM.2010.60. Paper Link

Z. Qi, J. Wang, A. Cabe, S. Wooters, T. Blalock, B. Calhoun, and M. Stan, “SRAM-Based NBTI/PBTI Sensor System Design,” in Proceedings of the 47th Design Automation Conference, 2010, pp. 849–852, doi: 10.1145/1837274.1837486. Paper Link

S. Nalam, M. Bhargava, K. Mai, and B. H. Calhoun, “Virtual Prototyper (ViPro): An early design space exploration and optimization tool for SRAM designers,” in Proceedings of the 47th Design Automation Conference, 2010, pp. 138–143, doi: 10.1145/1837274.1837310. Paper Link

B. H. Calhoun, S. Khanna, Y. Zhang, J. Ryan, and B. Otis, “System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavenging Mechanisms,” in Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010, pp. 269–272, doi: 10.1109/iscas.2010.5537887. Paper Link

S. N. Wooters, B. H. Calhoun, and T. N. Blalock, “An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 4, pp. 290–294, Apr. 2010, doi: 10.1109/TCSII.2010.2043471. Paper Link

S. Nalam, V. Chandra, C. Pietrzyk, R. C. Aitken, and B. H. Calhoun, “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation,” in 2010 11th International Symposium on Quality Electronic Design (ISQED), 2010, pp. 139–146, doi: 10.1109/ISQED.2010.5450400. Paper Link

R. W. Mann, S. Nalam, J. Wang, and B. H. Calhoun, “Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM,” in 2010 11th International Symposium on Quality Electronic Design (ISQED), 2010, pp. 1–8, doi: 10.1109/ISQED.2010.5450413. Paper Link

B. H. Calhoun, S. Arrabi, S. Khanna, Y. Shakhsheer, K. Craig, J. F. Ryan, and J. Lach, “REESES: Rapid Efficient Energy Scalable ElectronicS,” in Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2010, 2010.

B. H. Calhoun, J. F. Ryan, S. Khanna, M. Putic, and J. Lach, “Flexible Circuits and Architectures for Ultralow Power,” Proceedings of the IEEE, vol. 98, no. 2, pp. 267–282, Feb. 2010, doi: 10.1109/JPROC.2009.2037211. Paper Link

J. Wang and B. H., “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs,” in Solid State Circuits Technologies, 2010, doi: 10.5772/6876. Paper Link

M. Guevara, P. Wu, M. D. Marino, J. Meng, L. G. Szafaryn, P. Satyamoorthy, B. Meyer, K. Skadron, J. Lach, and B. Calhoun, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores,” in SRC TECHCON 2010, 2010.

2009

S. Nalam, M. Bhargava, K. Ringgenberg, K. Mai, and B. H. Calhoun, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes,” in 2009 IEEE International Conference on Computer Design, 2009, pp. 523–528, doi: 10.1109/ICCD.2009.5413107. Paper Link

M. Putic, L. Di, B. H. Calhoun, and J. Lach, “Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design,” in 2009 IEEE International Conference on Computer Design, 2009, pp. 491–497, doi: 10.1109/ICCD.2009.5413110. Paper Link | Chip Gallery

M. Bhargava, S. Nalam, B. H. Calhoun, and K. Mai, “An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization,” in SRC TECHCON 2009, 2009.

S. Nalam and B. H. Calhoun, “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T,” in 2009 IEEE Custom Integrated Circuits Conference, 2009, pp. 709–712, doi: 10.1109/CICC.2009.5280733. Paper Link | Chip Gallery

S. Khanna and B. H. Calhoun, “Serial Sub-threshold Circuits for Ultra-Low-Power Systems,” in Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 27–32, doi: 10.1145/1594233.1594241. Paper Link

B. H. Calhoun, J. Bolus, S. Khanna, A. D. Jurik, A. C. Weaver, and T. N. Blalock, “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors,” in 2009 IEEE International Symposium on Circuits and Systems, 2009, pp. 1437–1440, doi: 10.1109/ISCAS.2009.5118036. Paper Link

B. H. Calhoun, S. Khanna, R. Mann, and J. Wang, “Sub-threshold Circuit Design with Shrinking CMOS Devices,” in 2009 IEEE International Symposium on Circuits and Systems, 2009, pp. 2541–2544, doi: 10.1109/ISCAS.2009.5118319. Paper Link

M. A. Hanson, H. C. Powell, A. T. Barth, K. Ringgenberg, B. H. Calhoun, J. H. Aylor, and J. Lach, “Body Area Sensor Networks: Challenges and Opportunities,” Computer, vol. 42, no. 1, pp. 58–65, Jan. 2009, doi: 10.1109/MC.2009.5. Paper Link

Z. Qi, J. Wang, B. H. Calhoun, and M. R. Stan, “MSN: Memory Sensor for NBTI,” in SRC TECHCON 2009, 2009.

S. C. Jocke, J. F. Bolus, S. N. Wooters, A. D. Jurik, A. C. Weaver, T. N. Blalock, and B. H. Calhoun, “A 2.6-µW Sub-threshold Mixed-signal ECG SoC,” in 2009 Symposium on VLSI Circuits, 2009. Chip Gallery

J. Rabaey, “Optimizing Power @ Standby: Memory (Chapter 9),” in Integrated Circuits and Systems, 2009, pp. 233–248, doi: 10.1007/978-0-387-71713-5_9. Paper Link

J. Rabaey, “Optimizing Power @ Design Time: Memory (Chapter 7),” in Integrated Circuits and Systems, 2009, pp. 183–206, doi: 10.1007/978-0-387-71713-5_7. Paper Link

A. D. Jurik, J. F. Bolus, A. C. Weaver, B. H. Calhoun, and T. N. Blalock, “Mobile Health Monitoring Through Biotelemetry,” in Proceedings of the 4th International ICST Conference on Body Area Networks, 2009, doi: 10.4108/ICST.BODYNETS2009.5835. Paper Link

2008

J. Wang and B. H. Calhoun, “Techniques to Extend Canary-Based Standby VDD Scaling for SRAMs to 45 nm and Beyond,” IEEE Journal of Solid-State Circuits, vol. 43, no. 11, pp. 2514–2523, Nov. 2008, doi: 10.1109/JSSC.2008.2005814. Paper Link

L. Di, M. Putic, J. Lach, and B. H. Calhoun, “Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling,” in 2008 IEEE International Conference on Computer Design, 2008, pp. 605–611, doi: 10.1109/ICCD.2008.4751923. Paper Link

J. F. Ryan and B. H. Calhoun, “Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation,” in 9th International Symposium on Quality Electronic Design (isqed 2008), 2008, pp. 127–132, doi: 10.1109/ISQED.2008.4479712. Paper Link

B. H. Calhoun, Y. Cao, X. Li, K. Mai, L. T. Pileggi, R. A. Rutenbar, and K. L. Shepard, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS,” Proceedings of the IEEE, vol. 96, no. 2, pp. 343–365, Feb. 2008, doi: 10.1109/JPROC.2007.911072. Paper Link

A. Singhee, J. Wang, B. H. Calhoun, and R. A. Rutenbar, “Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design,” in 21st International Conference on VLSI Design (VLSID 2008), 2008, pp. 131–136, doi: 10.1109/VLSI.2008.54. Paper Link

J. Wang and B. H. Calhoun, “An Enhanced Adaptive Canary System for SRAM Standby Power Reduction,” in SRC TECHCON 2008, 2008. Chip Gallery

J. Wang, S. Nalam, and B. H. Calhoun, “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs,” in Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008, p. 129, doi: 10.1145/1393921.1393954. Paper Link

2007

J. Wang, A. Singhee, R. A. Rutenbar, and B. H. Calhoun, “Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array,” in ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, 2007, pp. 400–403, doi: 10.1109/ESSCIRC.2007.4430327. Paper Link

J. F. Ryan, J. Wang, and B. H. Calhoun, “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design,” in Proceedings of the 17th ACM Great Lakes symposium on VLSI, 2007, pp. 275–280, doi: 10.1145/1228784.1228853. Paper Link

B. H. Calhoun and A. P. Chandrakasan, “A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation,” IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 680–688, Mar. 2007, doi: 10.1109/JSSC.2006.891726. Paper Link | Chip Gallery

J. Wang and B. H. Calhoun, “Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM,” in 2007 IEEE Custom Integrated Circuits Conference, 2007, pp. 29–32, doi: 10.1109/CICC.2007.4405675. Paper Link | Chip Gallery

A. Wang, B. H. Calhoun, N. Verma, J. Kwong, and A. Chandrakasan, “Ultra-Dynamic Voltage Scaling for Energy Starved Electronics,” in Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2007, paper 34-1.

2006

A. Wang, B. H. Calhoun, and A. P. Chandrakasan, “Sub-threshold Design for Ultra Low-Power Systems,” in Springer, Series on Integrated Circuits and Systems, 2007, doi: 10.1007/978-0-387-34501-7. Paper Link

B. H. Calhoun and A. P. Chandrakasan, “Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 7, pp. 1673–1679, Jul. 2006, doi: 10.1109/JSSC.2006.873215. Paper Link

B. H. Calhoun and A. P. Chandrakasan, “Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-Threshold Operation and Local Voltage Dithering,” IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 238–245, Jan. 2006, doi: 10.1109/JSSC.2005.859886. Paper Link

A. Chandrakasan, N. Verma, J. Kwong, D. Daly, N. Ickes, D. Finchelstein, and B. Calhoun, “Micropower Wireless Sensors,” in Nanotech Conference and Expo 2006, 2006.

B. H. Calhoun and A. Chandrakasan, “A 256kb Sub-threshold SRAM in 65nm CMOS,” in 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, pp. 2592–2601, doi: 10.1109/ISSCC.2006.1696325. Paper Link

B. H. Calhoun, A. Wang, N. Verma, and A. Chandrakasan, “Sub-Threshold Design: The Challenges of Minimizing Circuit Energy,” in Proceedings of the 2006 international symposium on Low power electronics and design - ISLPED '06, 2006, p. 366, doi: 10.1145/1165573.1165661. Paper Link

B. H. Calhoun, C. Schurgers, A. Wang, and A. Chandrakasan, “Low Energy Digital Circuit Design (Chapter 4.1),” in Hardware Technology Drivers of Ambient Intelligence, 2006, pp. 181–202.

B. Calhoun, J. Kao, and A. Chandrakasan, “Power Gating and Dynamic Voltage Scaling (Chapter 3),” in Series on Integrated Circuits and Systems, pp. 41–75, doi: 10.1007/0-387-28133-9_3. Paper Link

2005

B. H. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits,” IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1778–1786, Sep. 2005, doi: 10.1109/JSSC.2005.852162. Paper Link

B. H. Calhoun, D. C. Daly, N. Verma, D. F. Finchelstein, D. D. Wentzloff, A. Wang, S.-H. Cho, and A. P. Chandrakasan, “Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes,” IEEE Transactions on Computers, vol. 54, no. 6, pp. 727–740, Jun. 2005, doi: 10.1109/TC.2005.98. Paper Link

B. H. Calhoun and A. Chandrakasan, “Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS,” in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., pp. 300–599, doi: 10.1109/ISSCC.2005.1493988. Paper Link

B. H. Calhoun and A. Chandrakasan, “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS,” in Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005., pp. 363–366, doi: 10.1109/ESSCIR.2005.1541635. Paper Link

2004

B. H. Calhoun and A. P. Chandrakasan, “Standby Power Reduction Using Dynamic Voltage Scaling and Canary Flip-Flop Structures,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1504–1511, Sep. 2004, doi: 10.1109/JSSC.2004.831432. Paper Link

B. H. Calhoun and A. Chandrakasan, “Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits,” in Proceedings of the 2004 international symposium on Low power electronics and design, 2004, pp. 90–95, doi: 10.1145/1013235.1013265. Paper Link

B. H. Calhoun, F. A. Honore, and A. P. Chandrakasan, “A Leakage Reduction Methodology for Distributed MTCMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp. 818–826, May 2004, doi: 10.1109/JSSC.2004.826335. Paper Link

E. Shih, S. Cho, F. S. Lee, B. H. Calhoun, and A. Chandrakasan, “Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks,” Journal of VLSI signal processing systems for signal, image and video technology, vol. 37, no. 1, pp. 77–94, May 2004, doi: 10.1023/B:VLSI.0000017004.57230.91. Paper Link

D. D. Wentzloff, B. H. Calhoun, R. Min, A. Wang, N. Ickes, and A. P. Chandrakasan, “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes,” in 17th International Conference on VLSI Design. Proceedings., pp. 361–367, doi: 10.1109/ICVD.2004.1260947. Paper Link

B. H. Calhoun, A. Wang, and A. Chandrakasan, “Device Sizing for Minimum Energy Operation in Subthreshold Circuits,” in Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), pp. 95–98, doi: 10.1109/CICC.2004.1358745. Paper Link

2003

B. H. Calhoun, F. A. Honore, and A. Chandrakasan, “Design Methodology for Fine-Grained Leakage Control in MTCMOS,” in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '03), Seoul, Korea, Aug. 25–27, 2003, 2003, p. 104.

B. Calhoun and A. Chandrakasan, “Standby Voltage Scaling for Reduced Power,” in Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., pp. 639–642, doi: 10.1109/CICC.2003.1249477. Paper Link

2002

P. Sotiriadis, O. Franza, D. W. Bailey, B. Calhoun, D. Lin, and A. Chandrakasan, “Fast Algorithm for Clock Grid Simulation,” in European Solid-State Circuits Conference, 2002.

2001

E. Shih, B. H. Calhoun, S. Cho, and A. P. Chandrakasan, “Energy-Efficient Link Layer for Wireless Microsensor Networks,” in Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, pp. 16–21, doi: 10.1109/IWV.2001.923134. Paper Link